The Use of Pre-Evaluation Phase in Dynamic CMOS Logic

Rao, A.; Haniotakis, T.; Tsiatouhas, Yiorgos; Djemil, H.

doi:10.1109/isvlsi.2005.72

Cited by 9 publications

(2 citation statements)

References 12 publications

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“…This configuration needs a pre‐charging structure, which may also be required in the rest of the system. Such a structure assumes a precharge phase large enough to meet the loading requirement of the logic on the system (case of dynamic‐logic systems which are more and more present in chips due to the increasing demand for speed 17). Therefore, this precharge structure does not imply any time overhead.…”

Section: Description Of the Pr‐insertion Methodologiesmentioning

confidence: 99%

A novel theory on parallel repeater‐insertion methodologies for long on‐chip interconnects

Awwad

Nekili

2011

Circuit Theory & Apps

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SUMMARYRepeaters are now widely used to enhance the performance of long on-chip interconnects in CMOS devices. For RC-as well as RLC-modeled interconnects, parallel repeaters (PRs) have proved to be superior to serial ones. In a previous work, a new regeneration technique, named variable-segment, was proven to outperform other existing regeneration techniques including variable-repeater techniques. In this paper, an approximate analytical delay model is presented for both the variable-repeater and variable-segment parallel regeneration techniques. This model is used to confirm the optimality of our design and is built based on first and second-moment transfer functions, which take into account the inductive effects of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using 0.25-m CMOS technology. The mathematical simulation results are remarkably in agreement with those obtained from electrically simulated variable-repeater and variable-segment structures which are used in this work to regenerate interconnect lengths ranging from 0.1 to 10 cm. This work is part of a first-of-its-kind global theory on PRs in repeater-insertion methodologies for long on-chip interconnects. This theory aims at exploring the different degrees of freedom in interconnect modeling as well as repeater type and design parameters.

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Section: Description Of the Pr‐insertion Methodologiesmentioning

confidence: 99%

A novel theory on parallel repeater‐insertion methodologies for long on‐chip interconnects

Awwad

Nekili

2011

Circuit Theory & Apps

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“…Moreover, a low-power differential current switch logic family has been introduced in [23]. Finally, low-power Domino logic designs, based on low-voltage swing techniques, have been presented in [24] and [25].…”

Section: Introductionmentioning

confidence: 99%

A Design Technique for Energy Reduction in NORA CMOS Logic

Limniotis

Tsiatouhas

Haniotakis

et al. 2006

IEEE Trans. Circuits Syst. I

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In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20% can be achieved. Simulation results from NORA designs in a 0.18-m CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction.Index Terms-Charge recycling, low-power design, NO RAce (NORA) CMOS circuits.

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Comprehensive analysis of linear phase frequency detectors in phase-locked loops

Sivaraaj,

K.K.

2024

AEU - International Journal of Electronics and Communications

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The Use of Pre-Evaluation Phase in Dynamic CMOS Logic

Cited by 9 publications

References 12 publications

A novel theory on parallel repeater‐insertion methodologies for long on‐chip interconnects

A novel theory on parallel repeater‐insertion methodologies for long on‐chip interconnects

A Design Technique for Energy Reduction in NORA CMOS Logic

Comprehensive analysis of linear phase frequency detectors in phase-locked loops

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