The vector-thread architecture

Abstract

The vector-thread (VT) architectural paradigm unifies the vector and multithreaded compute models. The VT abstraction provides the programmer with a control processor and a vector of virtual processors (VPs). The control processor can use vector-fetch commands to broadcast instructions to all the VPs or each VP can use thread-fetches to direct its own control flow. A seamless intermixing of the vector and threaded control mechanisms allows a VT architecture to flexibly and compactly encode application parallelism and locality, and a VT machine exploits these to improve performance and efficiency. We present SCALE, an instantiation of the VT architecture designed for low-power and high-performance embedded systems. We evaluate the SCALE prototype design using detailed simulation of a broad range of embedded applications and show that its performance is competitive with larger and more complex processors.

Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition

“…To evaluate data-parallel solutions, we used the Hwacha data-parallel accelerator with Rocket as its scalar control processor. The Hwacha data-parallel accelerator integrates ideas from both vector-thread [6,7] and conventional data-parallel processors to achieve high performance and energy efficiency. TFJ was used to generate optimized implementations for Rocket and Hwacha.…”

An OS-based alternative to full hardware coherence on tiled CMPs

“…In order to scale the number of cores in a CMP above this barrier, and into the numbers of cores proposed for tiled architectures [4,6,19,28,29], it is necessary to resort to scalable (i.e., point-to-point) interconnect types. Such interconnects are suitable not only because their peak bandwidth naturally scales with the number of cores, but also because, due to the short-length wires and low radix, their area overhead is a fixed, independent fraction of the number of cores.…”

“…There have been several proposals for tiled CMP architectures [4,6,19,28,29]. Most of these have focused on novel execution paradigms to exploit ILP and DLP in singlethreaded applications.…”

“…Either access latencies have to be significantly stretched or the area required by the interconnects has to be increased to the point of becoming impractical. Tiled CMPs [4,6,19,28,29] have been advocated as a possible alternative. Such systems are built from a relatively large number (≥ 32) of relatively simple cores plus a tightly integrated and lightweight point-to-point interconnect.…”

The design and implementation of a low-latency on-chip network

“…Of course, if a longer clock period is employed a smaller number of larger tiles may be used. Such tile-based systems may implement arrays of homogeneous processor/cache tiles [9], [10], finer-grain computing fabrics [14] or networks of heterogeneous IP blocks. Such approaches provide highly reconfigurable platforms for a wide range of performance hungry applications.…”