The Verilog® Hardware Description Language

Thomas, Donald E.; Moorby, Philip R.

doi:10.1007/978-1-4757-2896-5

Cited by 107 publications

(98 citation statements)

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“…A sound was produced on the FPGA and then it was output through an audio mini-Jack tied to the user I/O pin of the FPGA. The hardware description language [6] and Xilinx-ISE Project Navigator 10.1.03 were used for the circuit design. This system was evaluated by Logic Pro 8 which was used for recording the output and analyzing the waveforms.…”

Section: δς Conversion Methodsmentioning

confidence: 99%

A study of an FPGA synthesizer

Yoshida

Yamaguchi

2010

2010 International Conference on Audio, Language and Image Processing

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The mobile computing has been introduced to the general public and widely accepted at present. In the next stage, mobile computers enrich our lives and a lot of functions is required. High-performance synthesizers are eagerly anticipated to equip for mobile computing because it can help us and cheer up. Synthesizers are used for sound productions but then it requires enormous computational power. Therefore, each includes at least one digital signal processor but it is improper to mobiles. Here, this paper proposes a hardware synthesizer using a Field Programmable Gate Array (FPGA). The hardware synthesizer can bring high quality of the harmony and multiple simultaneous timbres. In addition, it can increase timbre of freedom and the analog circuits may be omitted from synthesizers.

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Section: δς Conversion Methodsmentioning

confidence: 99%

A study of an FPGA synthesizer

Yoshida

Yamaguchi

2010

2010 International Conference on Audio, Language and Image Processing

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“…Basically, design automation of digital circuits is a three-stage process that requires a formal description (high-level specification) of the system we would like to design and a toolbox (design kit) with the elementary functions (parts) that can be achieved with a given technology. The high-level specification is usually given through a description written in hardware description languages (HDL), such as VHDL (Ashenden, 2010) or Verilog (Thomas and Moorby, 2002). For example, the HDL description of a counter is a memory device that is incremented at each rising edge of a clock signal.…”

Section: Design Automation For Digital Electronicsmentioning

confidence: 99%

“…ODIN II requires a high-level specification provided in Verilog (Thomas and Moorby, 2002) or Berkeley Logic Interchange Format (BLIF) languages. The input interface bridges the gap between those specific languages and most common ways to describe a combinatorial digital system, such as a truth table or a set of Boolean equations.…”

Section: The Input Interfacementioning

confidence: 99%

GeNeDA: An Open-Source Workflow for Design Automation of Gene Regulatory Networks Inspired from Microelectronics

Madec

Pêcheux

Gendrault

et al. 2016

Journal of Computational Biology

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The topic of this article is the development of an open-source automated design framework for synthetic biology, specifically for the design of artificial gene regulatory networks based on a digital approach. In opposition to other tools, GeNeDA is an open-source online software based on existing tools used in microelectronics that have proven their efficiency over the last 30 years. The complete framework is composed of a computation core directly adapted from an Electronic Design Automation tool, input and output interfaces, a library of elementary parts that can be achieved with gene regulatory networks, and an interface with an electrical circuit simulator. Each of these modules is an extension of microelectronics tools and concepts: ODIN II, ABC, the Verilog language, SPICE simulator, and SystemC-AMS. GeNeDA is first validated on a benchmark of several combinatorial circuits. The results highlight the importance of the part library. Then, this framework is used for the design of a sequential circuit including a biological state machine.

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“…First, the image pixel data is read by the FPGA at a 25 MHz pixel clock rate. This data is then transferred to the Input Encoder function block inside the FPGA device, which contains the write-FIFO function, and implemented by Verilog HDL (Hardware Description Language) [8] code. To decrease the data transfer time between the SDAM and the FPGA, two 8-bit pixel data are combined into one 16-bit pixel data.…”

Section: Expermetial Setupmentioning

confidence: 99%

A low computing power frame rate converter

Chen

Liao

Chen

2012

2012 IEEE International Instrumentation and Measurement Technology Conference Proceedings

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A method of converting an unmatched image frame rate converter is presented. This low processing power method solves the problem of an unmatched frame rate between the image source and the instrument display apparatus, especially in a power limited condition. We used a Field Programmable Gate Array (FPGA) device as the design platform because of its flexibility and can be further transferred into Application specific integrated circuit (ASIC) to reduce the overall power consumption. The proposed design uses no power hungry arithmetic processing unit, such as multiplexer. Therefore, it is suitable for lowpower design, such as portable devices and hand-held instrument monitors.

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The Verilog® Hardware Description Language

Cited by 107 publications

References 0 publications

A study of an FPGA synthesizer

A study of an FPGA synthesizer

GeNeDA: An Open-Source Workflow for Design Automation of Gene Regulatory Networks Inspired from Microelectronics

A low computing power frame rate converter

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