The virtual chip set: a parametric IP library for system-on-a-chip design

Filippi, E.; Licciardi, L.; Montanaro, A.; Paolini, Maurizio; Turolla, M.; Taliercio, M.

doi:10.1109/cicc.1998.694915

Cited by 11 publications

(3 citation statements)

References 4 publications

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“…It offers a very complete tool suite to customize a base CPU considering the required instruction set. A different example is the VHDL IP library (VIP [7]): a library of parametric IP modules from CSELT. Each design in the library can be configured to match the final design requirements.…”

Section: Introductionmentioning

confidence: 99%

Soft-cores generation by instruction set analysis

Fin

Fummi

Perbellini

2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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The popularity of Soft Cores is rapidly increasing. Their integration in a design requires their synthesis and optimization, thus their application is more complex than the use of Hard Cores. However, Soft Cores can be customized to the design constraints, thus promising to lead to more efficient designs. The decision of using Soft or Hard Cores is difficult since it is a trade-off between performance, cost and design time. The parametrization methodology presented in this paper gives to the Soft Core providers the possibility of putting on the market easily customizable versions of their Cores. Moreover, the proposed Soft-Cores generator helps the designer to select between the Soft and the Hard-Core version of a processor.

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Section: Introductionmentioning

confidence: 99%

Soft-cores generation by instruction set analysis

Fin

Fummi

Perbellini

2001

Proceedings of the 14th International Symposium on Systems Synthesis - ISSS '01

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“…The VIP library™ has been used in the implementation of ICs and systems for ATM Switching and access nodes, Optical Network Units, Switched Digital Video Broadcast equipment [2]. The integration of the VIP modules in an industrial system or IC design flow usually requires minimum effort from the designer, who can focus his attention on the implementation of specific custom functionality.…”

Section: Ip Integrationmentioning

confidence: 99%

“…This paper describes our experience in designing an industrial test case using the POLIS HW/SW co-design methodology for embedded systems [1] and the CSELT VIP Library™ [2]. Our main goals have been the assessment of the effectiveness of POLIS for the design of embedded systems for telecom applications, and the definition of a methodology for the integration of system level IP libraries in the POLIS co-design framework.…”

Section: Introductionmentioning

confidence: 99%

Intellectual property re-use in embedded system co-design: an industrial case study

Filippi¹,

Lavagno²,

Licciardi³

et al.

Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210)

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Design of large systems on a chip would be infeasible without the capability to flexibly adapt the system architecture to the application and the re-use of existing Intellectual Property (IP). This in turn requires the use of an appropriate methodology for system specification, architecture selection, IP integration and implementation generation. The goals of this work are: a) verification of the effectiveness of the POLIS HW/SW co-design methodology for the design of embedded systems for telecom applications; b) definition of a methodology for integrating system level IP libraries in this HW/SW codesign framework. Methodology evaluations have been carried out through the development of an industrial telecom system design, an ATM node server.

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The virtual chip set: a parametric IP library for system-on-a-chip design

Cited by 11 publications

References 4 publications

Soft-cores generation by instruction set analysis

Soft-cores generation by instruction set analysis

Intellectual property re-use in embedded system co-design: an industrial case study

Block-level Verification

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