With continued shrinkage of circuit dimensions, the technique of chemical mechanical planarization (CMP) has become progressively more intricate through the last decade. Since the chemical mechanism of metal CMP is governed by electrochemical effects, the complex task of CMP-slurry engineering can be economically assisted in the electroanalytical approach by using laboratory scale model systems. This article discusses how CMP has been impacted by device scaling, and examines the status of fundamental studies of metal CMP. The techniques suitable for studying model CMP systems are discussed, along with an assessment of the utilities and the practical limits of such experiments. Chemical mechanical planarization (CMP) is an essential processing step of integrated circuit (IC) fabrication. 1,2 CMP of the metal components of logic devices constitute a major aspect of this technique and, like other areas of IC manufacturing, metal CMP has become quite complex while addressing the emerging demands of technology through the last decade. 3 The new challenges of metal CMP originate from both the scaling and the novel material aspects of these systems. 3,4 At the same time, published reports indicate that, many of these issues, especially those related to the slurry consumables, 5 can be addressed to a large extent through electroanalytical examinations of slurry functions using scaled down models of actual CMP systems. 6 Recent studies performed in industrial facilities have also identified a critical need to further advance the fundamental understanding of metal CMP. 7,8 The present article provides a perspective on these fundamental research aspects of metal CMP that are in the core of most laboratory scale studies of these systems.
Device Scaling and CMP ConsiderationsThe International Technology Roadmap for Semiconductors (ITRS) specified the earlier technology nodes in terms of the DRAM half-pitch (hp), or the microprocessor's level-1 metal hp of a device. 9 Basically until the 65 nm node, the shrinkage of feature-size has continued in line with Dennard scaling, by a factor (S) of 1/ √ 2, to accommodate doubling of transistors per unit chip area (scaling as S 2 = 1/2) every two years in relation to Moore's law. 10 Increased leakage currents in the subsequent feature reductions have eventually shifted this technology trend, with the emergence of advanced multicore systems. 11 While the scaling factor of 1/ √ 2 has been largely maintained in the post-Dennard period, the newer logic devices have evolved in a more complex manner compared to their earlier counterparts. The middle-of-line (MOL) metallization scheme has emerged from the need to reduce the parasitic effects of active wiring that extends over 4 km cm −2 for >13 metal layers. 9 Novel diffusion barriers and ultra-low-k (ULK) dielectrics, Fin field effect transistors (Fin-FETs), high-k gate dielectrics, and exploratory designs/materials for local interconnects have been steadily incorporated in new device architectures in keeping with the advents of scaling sch...