The XPP Architecture and Its Co-simulation Within the Simulink Environment

Petrov, M.; Murgan, T.; May, F.; Vorbach, Martin; Zipf, Peter; Glesner, Manfred

doi:10.1007/978-3-540-30117-2_77

Cited by 18 publications

(6 citation statements)

References 3 publications

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“…Input/Output data is directly transferred at the edge of the PE array directly to/from each PE or distributed memory modules. Figure 2 shows an array of PACT Xpp-64 [5]. 8 × 8 computational PE (ALU-PAE) are connected with 2 dimensional mesh, and at the both sides, memory modules (RAM-PAEs) for storing data are provided.…”

Section: Pe Array Structurementioning

confidence: 99%

A Survey on Dynamically Reconfigurable Processors

Amano¹

2006

IEICE Transactions on Communications

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Section: Pe Array Structurementioning

confidence: 99%

A Survey on Dynamically Reconfigurable Processors

Amano¹

2006

IEICE Transactions on Communications

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“…With its efficiency and flexibility, the DRPA as an off-loading engine will offer a low-power area-efficient design solution. Some devices are commercially available [1,2,3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays

Tsutsumi

Tunbunheng

Hasegawa

et al. 2007

2007 International Conference on Field-Programmable Technology

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A new configuration scheduling algorithm in multicast configuration scheme is proposed and evaluated over reduction ratio of configuration data transfer cycles and powerlenergy overhead on a coarse-grained dynamically reconfigurable processor array (DRPA). As a case study, the proposed methods are applied to some real applications on a DRPA architecture MuCCRA-1. As a result, we confirmed that the proposed overwrite configuration technique for DRPAs reduced an application configuration cycles 66.5% at maximum compared to one without multicast and 20.2% compared to one without the overwrite configuration. It also decreased the configuration energy consumption 18. 7% at maximum beyond the overhead of memory overwrites.

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“…Some devices are commercially available [1], [2], [3], [4], and some of them have been integrated into digital appliances.…”

Section: Introductionmentioning

confidence: 99%

A study on interconnection networks of the Dynamically Reconfigurable Processor Array MuCCRA

Kato

Sano

Yoshihiro

et al. 2009

2009 International Conference on Field-Programmable Technology

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A Dynamically Reconfigurable Processor Array (DRPA) is consisting of a number of PEs, and its interconnection of PE array gives a large effect on the total area, energy and performance. However, there is no study of DRPAs focused on their PE network. In this paper, we designed four types of DRPAs based on MuCCRA, developed in MuCCRA(Multi-Core Configurable Reconfigurable Architecture) project. They have different topologies, which are direct interconnection, island-style interconnection and two kinds of hybrid interconnection. They are evaluated using three different PE array sizes. As a result, a MuCCRA with hybrid network, which has the highest degree of connectivity, is able to execute DCT faster than the other MuCCRAs, but requires more area by 20% than MuCCRA with direct network. On energy consumption, MuCCRA with direct links consumes 7 times more energy at maximum than islandstyle-interconnected MuCCRAs.

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The XPP Architecture and Its Co-simulation Within the Simulink Environment

Cited by 18 publications

References 3 publications

A Survey on Dynamically Reconfigurable Processors

A Survey on Dynamically Reconfigurable Processors

Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays

A study on interconnection networks of the Dynamically Reconfigurable Processor Array MuCCRA

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