Theoretical Analysis and Implementation of Effective Receivers for Telecommand Space Links

Abstract

This paper deals with the feasibility of the new receiver scheme for telecommand space links, based on the adoption of short low-density parity-check codes recently introduced in the standard. Being able to reduce significantly the required signal-to-noise ratio, these codes have an impact on the acquisition, tracking and synchronization issues. All these aspects have been faced, both theoretically and practically through the realization of a breadboard that implements the core elements of the on-board receiver, and is able to demodulate and decode uplink signals employing the new codes. The breadboard incorporates innovative solutions to cope with the acquisition and synchronization problems, and a pioneering implementation of non-iterative decoders based on the most reliable basis algorithm.

Next generation earth-to-space telecommand coding and synchronization: ground system design, optimization and software implementation

“…A Field-Programmable Gate Array (FPGA) implementation of the in-space TC receiver, working in real time, was presented in [9,10]. In contrast, in this paper we address the ground segment transmission chain.…”

“…The reason why LDPC codes need longer start sequences is that, thanks to their coding gain, they are able to work at lower SNR. Then, a longer sequence is used to reliably acquire CLTU synchronization [9,10]. The CLTU generation block may also append a tail sequence for some configurations:…”

“…5555 5556 AAAA AAAA 5555 5555 5555 5555 HEX may be appended. In particular, this tail sequence is mandatory if we want to apply decoders based on Most Reliable Basis (MRB) [15] for LDPC complete decoding [9,10]. • For the LDPC(512, 256) code, no tail sequence is appended (in fact, the MRB complexity becomes intractable for this code).…”

“…Obviously, the new codes require an extra-complexity both at the ground station transmitter and at the on-board receiver. The results of a study on the design and real-time implementation of the on-board receiver were presented in [9,10].…”

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

“…Regarding the development of the baseband receiver, we presented a preliminary work in [11], which focused on the frame synchronization module. Indeed, the authors of [12] have identified the frame synchronization process as one of the most critical aspects of the receiving chain, which creates a bottleneck. In Earth observation missions, the amount of collected data to be delivered to ground stations has reached several terabytes per day [13].…”