2016 IEEE International 3D Systems Integration Conference (3DIC) 2016
DOI: 10.1109/3dic.2016.7969996
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Thermal analysis of multi-layer functional 3D logic stacks

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Cited by 6 publications
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“…Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips. This is a common scenario in 3D package platforms such as TSV-SIP (through silicon via) and HBM [94][95][96][97][98][99][100][101][102][103]. These two categories of thermal management challenges are reviewed in Secs.…”
Section: Thermal Management Challenges In Heterogeneousmentioning
confidence: 99%
“…Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips. This is a common scenario in 3D package platforms such as TSV-SIP (through silicon via) and HBM [94][95][96][97][98][99][100][101][102][103]. These two categories of thermal management challenges are reviewed in Secs.…”
Section: Thermal Management Challenges In Heterogeneousmentioning
confidence: 99%