Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability

Gupta, Aseem; Dutt, Nikil; Kurdahi, Fadi; Khouri, K.S.; Abadir, Magdy S.

doi:10.1109/isqed.2008.4479779

Cited by 10 publications

(16 citation statements)

References 15 publications

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“… Our reliability-aware router significantly outperforms the previous work [9]. On ISPD98 benchmark suite, it reduces the system failure rate by 13% without sacrificing routability, and under tiny runtime and wire length overhead.…”

Section: Introductionmentioning

confidence: 83%

“…Followed by reliability-aware L-shape routing, it quickly determines whether a net can be entirely routed under certain capacity constraints. But instead of considering the maximum temperature on the paths like that was done in [9], we evaluate the contribution of the candidate paths to system reliability in order to choose one path over another. Finally, we apply maze routing to the remaining nets and it requires several iterations before the router can find a high quality solution in terms of the metric we defined.…”

Section: Reliability-aware Global Routingmentioning

confidence: 99%

“…The previous work in [9] uses maximum temperature on a given path as its metric in determining the superiority of one routing path over another in terms of reliability. It decreases the worst-case failure rate of a two-pin connection by selecting the path with a smaller cost (i.e.…”

Section: Reliability Metricmentioning

confidence: 99%

“…A recent work in [9] proposed a Lshape approach for the problem, which suggested evaluating the two alternative paths during L-shape routing and choosing the path with a lower maximum temperature. However, L-shape routing is only a part of the routing flow and they did not consider the temperature factor in any other phases.…”

Section: Introductionmentioning

confidence: 99%

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Reliability-aware global routing under thermal considerations

Pan

2009

2009 1st Asia Symposium on Quality Electronic Design

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Thermal effect is a key factor to interconnect reliability degradation. As technology scales, the distance between the metal layers and substrate continues to shrink and significantly increases the impact of substrate temperature on interconnect reliability. While it is already a concern in 2D ICs, the thermal impact will be more challenging in the emerging 3D ICs architecture. In this paper, we present a reliability-aware global routing with thermal considerations. We propose two techniques, thermal-driven Minimum Spanning Tree (MST) construction and thermal-driven maze routing, to reduce the probability of interconnect failures. Experimental results show that our router effectively reduces the failure rate by approximately 13% on average, with little overhead on the traditional design objectives.

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Section: Introductionmentioning

confidence: 83%

Section: Reliability-aware Global Routingmentioning

confidence: 99%

Section: Reliability Metricmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Reliability-aware global routing under thermal considerations

Pan

2009

2009 1st Asia Symposium on Quality Electronic Design

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“…While in [3], optimal insertion of tunable delay buffers into clock trees is discussed to adjust at run time the delay of clock distribution paths that are more susceptible to temperature variations. Thermal aware global routing algorithms for improving reliability are also discussed in [4], [5]. On the other side, regarding global signal wires, although extensive work has been done on thermal aware floorplanning, all of them assume electrical resistivity in wires is constant and thermal gradients in the substrate has no impact on wire delay.…”

Section: Introductionmentioning

confidence: 99%

Temperature dependent wire delay estimation in floorplanning

et al. 2011

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Abstract-Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this work, we show that using wirelength as the evaluation metric does not always produce a floorplan with the shortest delay. We propose a temperature dependent wire delay estimation method for thermal aware floorplanning algorithms, which takes into account the thermal effect on wire delay. The experiment results show that a shorter delay can be achieved using the proposed method. In addition, we also discuss the congestion and reliability issues as they are closely related to routing and temperature.

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Thermal characterization and challenges of advanced interconnects (Invited)

Kim

Christiansen

et al. 2016

2016 IEEE International Reliability Physics Symposium (IRPS)

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Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability

Cited by 10 publications

References 15 publications

Reliability-aware global routing under thermal considerations

Reliability-aware global routing under thermal considerations

Temperature dependent wire delay estimation in floorplanning

Thermal characterization and challenges of advanced interconnects (Invited)

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