Thermal Barrier Phase Change Memory

Abstract

Phase change memory is widely considered as the most promising candidate as storage class memory (SCM), bridging the performance gaps between dynamic random access memory and flash. However, high required operation current remains the major limitation for the SCM application, even after using defect engineering materials, for example, Ti-doped Sb 2 Te 3 . Here, we demonstrate that ∼87% current can be reduced by spatially separating Sb 2 Te 3 and TiTe 2 layers, thanks to semimetallic TiTe 2 serving as a thermal barrier in the reset process. Moreover, the stable crystalline TiTe 2 layer provides an ordered interface to speed up the crystallization process of the amorphous Sb 2 Te 3 layer, enabling ∼10 ns ultrafast crystallization speed. An outstanding device lifetime, up to ∼2 × 10 7 cycles, has been obtained, which is twice as long as that of alloy-based cells. Correlative electron microscopy and atom probe tomography provide evidence that the TiTe 2 /Sb 2 Te 3 multilayer can keep a layer-stacked structure, avoiding phase segregation found in alloys and strong element intermixing in the GeTe/Sb 2 Te 3 superlattice, which enables excellent cyclability. This study suggests that adding a semimetallic layer in the phase change layer, such as TiTe 2 and TiSe 2 , can yield a phase change memory with superior properties. KEYWORDS: thermal barrier phase change material, atom probe tomography, Ti−Sb−Te, TiTe 2 , TiTe 2 /Sb 2 Te 3 , high endurance, low energy consumption

Scalability of Sulfur‐Based Ovonic Threshold Selectors for 3D Stackable Memory Applications

“…[24] Noticeably, although the reset current of the PCM cell can be reduced to microampere scale with feature size smaller than 180 nm, the corresponding current density increases remarkably as the device size shrinks. [25][26][27] This means that S-based OTS cells should have similar scaling behavior for sufficiently programming the nanometer-scale PCM cells, which has still not been reported yet. Therefore, in this work, we first investigate the scalability of GeS OTS selector as the device scales down from 200 to 60 nm, including the threshold/hold voltage, ON/OFF switching speed, ON/OFF current, and ON current density.…”

Interface controlled thermal resistances of ultra-thin chalcogenide-based phase change memory devices

“…Later, Ahn et al 7 proposed a much thinner insulating layer by using a single sheet of graphene (thickness <1 nm) as a thermal barrier to isolate the heat inside the PCM cell and showed that the I reset was reduced by 40% compared to the cells without a graphene barrier. More recently, superlattice phase change memories have received a great deal of attention due to their unique capabilities offering lower power consumption, faster programming rate, higher retention time, and lower noise and drift in electrical resistance 3,[8][9][10] . Although earlier superlattice PCMs consisted of GeTe/Sb 2 Te 3 alternating stacks, it was soon realized that this configuration tends to intermix and transform into bulk GST at high annealing temperatures 11 .…”

“…Nonetheless, the idea of superlattice PCMs inspired researchers to look for alternative material configurations. Very recently, Shen et al 8 and Ding et al 9 showed that superlattice PCMs with TiTe 2 /Sb 2 Te 3 layers have superior properties compared to bulk GST. Despite the fact that in superlattice PCMs the interface is an integral component in the performance of these devices, its effect on the overall thermal transport is heretofore unknown and unstudied.…”

Reliable 2D Phase Transitions for Low-Noise and Long-Life Memory Programming

“…The SLL-based device underwent repeated 3D phase transitions up to ∼10 7 cycles until SET sticking failure took place (Figure 4A). We note similar SLL-based device also presented an approximate endurance (Shen et al, 2019), but showing considerably larger resistance fluctuations in both RESET and SET states than those of the SLLbased device studied in this work. The relative standard deviations (RSDs) of RESET and SET states of the SLL-based device are 6.3% (Figure 4C) and 2.2% (Figure 4D), respectively.…”