Thermal Instability of Effective Work Function in Metal/High-<tex>$kappa$</tex>Stack and Its Material Dependence

Abstract

Thermal instability of effective work function and its material dependence on metal/high-gate stacks is investigated. It is found that thermal instability of the effective work function of metal electrode on a gate dielectric is strongly dependent on the gate electrode and dielectric material. Thermal instability of a metal gate is related to the presence of silicon at the interface, and the Fermi-level pinning position is dependent on the location of silicon at the interface. The silicon-metal or metal-silicon bond formation by thermal anneal at the metal/dielectric interface induces the donor-like or acceptor-like interface states, causing a change of effective work function. Index Terms-Fermi-level pinning, high-, metal gate, thermal instability, work function.

Physical Characterization of the Metal/High-k Layer Interaction upon Annealing

“…At the same time, it was widely reported that the WF of a metal gate can shift significantly after thermal treatment (11,12,13,14). The difficulties to control and understand the WF of metal gates have been the subject of many studies (8,7,15,16).…”

Flatband voltage shift of ruthenium gated stacks and its link with the formation of a thin ruthenium oxide layer at the ruthenium/dielectric interface

“…[11][12][13][14] To study if the WF shift of Ru based gates is dependent on a high temperature anneal history or not, one sample was subjected to a 1000°C 1 s N 2 anneal before the standard FGA ͑to simulate the dopant activation process͒. The sample has the same structure as the one discussed in Sec.…”

“…At the same time, it was widely reported that the WF of a metal gate can shift significantly after thermal treatment. [11][12][13][14] The difficulties to control and understand the WF of metal gates have been the subject of many studies. 7,8,15,16 Many models, including metal-induced gate state 7,17 and dipole formation 16,18 have been employed to explain the physics behind WF, although no universal models have been widely accepted.…”

Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

“…1-4 On the other hand, Fermi-level pinning phenomenon becomes a critical issue when high-K gate dielectric is employed. 5,6 Metal-induced gap states ͑MIGS͒ theory is most widely used to analyze and predict the behavior of effective work function ͑⌽ m,eff ͒ in metal/ high-K dielectric gate stack. 7,8 Up to date, however, the application of MIGS theory to FUSI gate/high-K dielectric stack has not been attempted because of lack of information on vacuum work function of metal silicide ͑⌽ MSi x ͒ on high-K gate dielectric which is affected by stoichiometry of metal silicide at the high-K dielectric interface.…”