Thermal-mechanical fatigue reliability of pbsnag solder layer of die attachment for power electronic devices

Xie, Xinpeng; Bi, Xiangdong; Li, Guoyuan

doi:10.1109/icept.2009.5270615

Cited by 8 publications

(5 citation statements)

References 10 publications

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“…Solder fatigue is mainly due to differences in CTEs between the solder and the connected materials, as well as between different pads, resulting in solder delamination [47,48].…”

Section: Main Failure Modes and Characterization Parametersmentioning

confidence: 99%

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Huang,

Singh,

Liu

et al. 2024

Energies

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Silicon carbide (SiC)-based metal–oxide–semiconductor field-effect transistors (MOSFETs) hold promising application prospects in future high-capacity high-power converters due to their excellent electrothermal characteristics. However, as nascent power electronic devices, their long-term operational reliability lacks sufficient field data. The power cycling test is an important experimental method to assess packaging-related reliability. In order to obtain data closest to actual working conditions, forward power cycling is utilized to carry out SiC MOSFET degradation experiments. Due to the wide bandgap characteristics of SiC MOSFETs, the short-term drift of the threshold voltage is much more serious than that of silicon (Si)-based devices. Therefore, an offline threshold voltage measurement circuit is implemented during power cycling tests to minimize errors arising from this short-term drift. Different characterizations are performed based on power cycling tests, focused on measuring the on-state resistance, thermal impedance, and threshold voltage of the devices. The findings reveal that the primary failure mode under forward power cycling tests, with a maximum junction temperature of 130 ∘C, is bond-wire degradation. Conversely, the solder layer and gate oxide exhibit minimal degradation tendencies under these conditions.

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“…Solder fatigue is mainly due to differences in CTEs between the solder and the connected materials, as well as between different pads, resulting in solder delamination [47,48].…”

Section: Main Failure Modes and Characterization Parametersmentioning

confidence: 99%

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Huang,

Singh,

Liu

et al. 2024

Energies

View full text Add to dashboard Cite

show abstract

“…In this framework, l 0 values have been selected equal to the solder length. The four parameters K i have been chosen according to literature source: [16] for PbSnAg and [19] for SnAgCu as shown in table 3.…”

Section: Fatigue Analysismentioning

confidence: 99%

“…Two representative methodologies are the Morrow [14] and Darveaux [15] approaches. The dissipated energy is calculated by FEA and lifetime solder prediction can be forecast once model calibration with experimental reliability test on the same solder compound or according to literature results [16] .…”

Section: Introductionmentioning

confidence: 99%

Power Semiconductor Devices and Packages: Solder Mechanical Characterization and Lifetime Prediction

et al. 2021

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Solder reliability is a key aspect for the packaging of low voltage power semiconductor device. The interconnections among package components, e.g. the silicon chip and copper leadframe, and between package itself and the external printed control board (PCB) should be properly designed to ensure the automotive durability requirements. In this framework, the proposed paper introduces an experimentalnumeric characterization flow with the purpose to analyze solder visco-plasticity and fatigue during passive temperature cycle. The presented methodology has included solder mechanical characterization aimed to determine the parameters of Anand model which reproduces the solder visco-plastic behavior and the mechanical properties' temperature dependency. Finite element model has been employed to calculate the inelastic work which solder dissipates during each temperature cycle. Simulation results serve as input to predict solder lifetime according to an energetic method. Moreover, failure analyses have been performed to assess the failure mechanism and to check model correlation in terms of number of cycles to failure forecast.

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“…For example, when Otiaba et al performed a thermal mechanical coupling analysis on a three-layer structure consisting of a chip, solder, and copper substrate (with constraints placed on the top of the chip), they found that the stresses in the solder joints varied monotonically with temperature loading in a periodic manner [3]. While Xie et al performed a similar simulation (with constraints placed on the bottom of the copper layer), a small stress recovery peak was observed during the heating up stage [20]. Similar stress recovery phenomena can often be seen in temperature cycling simulations, but there is no clear explanation for their formation mechanism and the reasonability [21,22].…”

Section: Introductionmentioning

confidence: 99%

Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

et al. 2021

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Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

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Thermal-mechanical fatigue reliability of pbsnag solder layer of die attachment for power electronic devices

Cited by 8 publications

References 10 publications

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Failure Characterization of Discrete SiC MOSFETs under Forward Power Cycling Test

Power Semiconductor Devices and Packages: Solder Mechanical Characterization and Lifetime Prediction

Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

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