2012 13th International Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems 2012
DOI: 10.1109/esime.2012.6191797
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Thermal-mechanical responses of 3D IC integration with a passive TSV interposer

Abstract: In this study, 3D IC integrations with a TSV interposer supporting Moore's law chips on its top and bottom sides are investigated. Emphasis is placed on the determination of the TSV interposer warpage and the nonlinear stress and creep strain in the Cu-Iow-k pads and micro solder joints.

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Cited by 4 publications
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“…Therefore, 3D IC with through silicon via (TSV) becomes a inevitable product for high density and high performance operations. In recent years, the researches of 3D IC are mainly focused on the relevant issues including front end of line for wafer handling [1], TSV manufacturing and characterization [2][3][4], novel package process [5][6], micro-bump design and bondability [7][8][9], reliability test and analysis [10][11][12]. However, as a result of high-cost, technique barriers, and low yields, 3D IC is still difficult to be a general productive product at present.…”
Section: Introductionmentioning
confidence: 99%
“…Therefore, 3D IC with through silicon via (TSV) becomes a inevitable product for high density and high performance operations. In recent years, the researches of 3D IC are mainly focused on the relevant issues including front end of line for wafer handling [1], TSV manufacturing and characterization [2][3][4], novel package process [5][6], micro-bump design and bondability [7][8][9], reliability test and analysis [10][11][12]. However, as a result of high-cost, technique barriers, and low yields, 3D IC is still difficult to be a general productive product at present.…”
Section: Introductionmentioning
confidence: 99%