Thermal Modeling, Characterization and Management of On-Chip Networks

Shang, Li; Peh, Li-Shiuan; Kumar, Amit; Jha, Niraj K.

doi:10.1109/micro.2004.35

Cited by 132 publications

(71 citation statements)

References 27 publications

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“…The state-of-art related schemes mainly include global throttling (GT) [5], distributive throttling (DT) [6] and vertical throttling (VT) [4,7]. When a node is in thermal emergent state, they would globally, distributively or vertically throttle the router nodes, respectively.…”

Section: Introductionmentioning

confidence: 99%

ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation

Gao

Feng

et al. 2017

IEICE Electron. Express

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Three dimensional (3D) networks-on-chip (NoCs) is beneficial to performance improvement, but suffers severe thermal issues. Because of the fast packet switching activity and small area, an NoC router might even show higher power density than a process element, quite easily forming a thermal hotspot. Throttling based dynamic thermal managements (DTMs) help for fast cooling, but easily results in network congestion and introduces large cost. This paper proposed an efficient routing-based DTM scheme (ArR-DTM), which tries to balance the thermal distribution by providing complementary adaptive degree for lateral planes and finish thermal migration by regulating the adaptive degree in vertical direction. Experiments show that, under the same thermal limit, there is 13.1% to 23.8% performance improvement compared to the fully throttling based DTMs.

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Section: Introductionmentioning

confidence: 99%

ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation

Gao

Feng

et al. 2017

IEICE Electron. Express

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“…To minimize the power consumption of on-chip interconnects, recent research proposes circuit-level techniques to improve the power efficiency of the link circuitry and the router microarchitecture [17], dynamic voltage scaling [13] and power management [13,14], and thermal-aware routing [15]. However, these prior works miss one crucial observation: a large fraction of the on-chip interconnect traffic stems from packets sent to enforce data coherence, rather than from packets absolutely required to facilitate data sharing.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores

Schuchhardt¹,

Hardavellas²,

Memik³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-On-chip interconnection networks consume a significant fraction of the chip's power, and the rapidly increasing core counts in future technologies is going to further aggravate their impact on the chip's overall power consumption. A large fraction of the traffic originates not from data messages exchanged between sharing cores, but from the communication between the cores and intermediate hardware structures (i.e., directories) for the purpose of maintaining coherence in the presence of conflicting updates. In this paper, we propose Dynamic Directories, a method allowing the directories to be placed arbitrarily in the chip by piggy-backing the virtual to physical address translation. This eliminates a large fraction of the on-chip interconnect traversals, hence reducing the power consumption. Through trace-driven and cycle-accurate simulation in a range of scientific and Map-Reduce applications, we show that our technique reduces the power and energy expended by the on-chip interconnect by up to 37% (16.4% on average) with negligible hardware overhead and a small improvement in performance (1.3% on average). 21

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“…In [58], authors propose ThermalHerd, a distributed, collaborative run-time thermal management scheme for on-chip networks to tackle thermal emergencies ensuring thermal safety with little performance impact. Every router is equipped with a set of registers (or counters) to estimate the traffic workload and the temperature sensor to adjust the traffic, but they only support minimal path routing.…”

Section: Routing Algorithmsmentioning

confidence: 99%

Cost Effective Routing Implementations for On-chip Networks

Mocholi¹

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Thermal Modeling, Characterization and Management of On-Chip Networks

Abstract: Abstract

Cited by 132 publications

References 27 publications

ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation

ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation

Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores

Cost Effective Routing Implementations for On-chip Networks

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