Thermal stress destruction analysis in low-k layer by via-last TSV structure

Kitada, Hideki; Akamatsu, Tomonari; Mizushima, Y.; Ishitsuka, Takeshi; Sakuyama, Seiki

doi:10.1109/ectc.2015.7159850

Cited by 9 publications

(6 citation statements)

References 13 publications

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“…That thermal stress delaminates the interface between copper and silicon. 2 It also causes stress and cracks in the surrounding silicon. 2,3 The thermal stress of copper TSV has been studied with different structural designs, such as the impacts of TSV diameter 4,5 and TSV geometry.…”

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confidence: 99%

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Thermal Stress Reduction of Copper Through Silicon Via (TSV) with Annealing

Dinh¹,

Kondo²,

Hoang³

et al. 2018

ECS J. Solid State Sci. Technol.

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Electrodeposited copper is widely used in TSV filling due to its low resistivity. Unfortunately, its TEC of 17 × 10 −6 / • C causes thermal stress during annealing due to the mismatch with silicon TEC of 2 × 10 −6 / • C. In the upper region of the TSV, stress is released by the extrusion of copper when annealing. The results showed the extrusion height of copper TSV increases with the increase of temperature and the extrusion height is about 1.2 μm at 500 • C for conventional copper TSV. Also, at via the bottom corner, this stress due to the mismatch in TEC between copper and silicon is accumulated. That stress is the reason for the cracks at the bottom corner of the conventional copper TSV. With our low TEC copper, the extrusion height of copper decreases to only 0.3 μm and no cracks occur at the via bottom corner. In addition, the resistivity values of low TEC copper are always lower than that of conventional copper in as electrodeposited copper and after annealing at different temperatures. The results suggest that the low TEC copper is not only good at reducing thermal stress in TSV due to annealing but also decreasing the resistivity of copper TSV.

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“…2 It also causes stress and cracks in the surrounding silicon. 2,3 The thermal stress of copper TSV has been studied with different structural designs, such as the impacts of TSV diameter 4,5 and TSV geometry. 5 According to K. H. Lu research, 4 the larger the TSV diameter, the greater the stress acting on the surrounding silicon.…”

mentioning

confidence: 99%

Thermal Stress Reduction of Copper Through Silicon Via (TSV) with Annealing

Dinh¹,

Kondo²,

Hoang³

et al. 2018

ECS J. Solid State Sci. Technol.

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“…For example, at room temperature the ITCs between common metals (e.g. Au, Al, and Ag) and graphene range from ~30 to 100 MW m -2 K -1 (figure 8(a)) [146,266,[349][350][351][352][353], whereas the ITCs of metal/silicon interface are typically >150 MW m -2 K -1 , and the phonon ITC of epitaxial solid/solid interfaces can reach ~700 MW m -2 K -1 [354,355]. Similarly, the ITCs between metals and another 2D material, MoS 2 , are even lower, 20-26 MW m -2 K -1 [356].…”

Section: Interfacial Thermal Conductance Between 2d/3d and 2d/2d Mate...mentioning

confidence: 99%

Advances in thermal conductivity for energy applications: a review

et al. 2021

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Thermal conductivity is a crucial material property for a diverse range of energy technologies, ranging from thermal management of high power electronics to thermal insulation for building envelopes. This review discusses recent advances in achieving high and low thermal conductivity (k) as relevant for energy applications, from high-k heat spreaders to low-k insulation. We begin with a brief introduction to the physics of heat conduction from both theoretical and computational perspectives. The heart of the review is a survey of recent advances in high- and low-k materials. The discussion of good heat conductors for thermal management includes inorganics and polymers in both bulk and low dimensional forms. For insulators, the discussion covers the effects of chemical composition, crystal structure, and defects and porosity. Promising areas for future research in both fundamental materials science and engineering technologies are noted.

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“…However, due to the large TEC mismatch between the silicon substrate and copper, copper expands 8 times larger than silicon, resulting in high thermal stresses in all directions during the manufacturing process. These thermal stresses of copper through-silicon via (TSV) lead to copper pumping, 1-3 cracking, 1,4,5 and delamination. 6,7 Low TEC of copper has been reported only by V.Q.…”

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confidence: 99%

Communication—A Rotating Ring Disk Study to Monitor the Concentration of 2M5S in Copper Low TEC Electrolytes

Tran

Hirato

Kondo

2021

J. Electrochem. Soc.

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A leveller additive, 2-mercapto-5-benzimidazolesulfonic acid (2M5S), is characterized and monitored by cyclic voltammetry stripping (CVS) measurements using a rotating ring disk electrode (RRDE). The ring current gradually decreases with the increase of 2M5S concentration from 1 to 8 ppm. The relationship between the ring current and 2M5S concentration is used for determining the deterioration of the low thermal expansion coefficient (TEC) copper electrodeposition solution. The amount of 2M5S in the 20-hour-electrolyzed solution has been monitored then supplied. The copper pipe electrodeposited with the refreshed solution achieved low TEC, approximately the same as the copper pipe electrodeposited with the fresh solution.

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Thermal stress destruction analysis in low-k layer by via-last TSV structure

Cited by 9 publications

References 13 publications

Thermal Stress Reduction of Copper Through Silicon Via (TSV) with Annealing

Thermal Stress Reduction of Copper Through Silicon Via (TSV) with Annealing

Advances in thermal conductivity for energy applications: a review

Communication—A Rotating Ring Disk Study to Monitor the Concentration of 2M5S in Copper Low TEC Electrolytes

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