Thermal synergies in 50 nanometer CMOS and below

Abstract

An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<�100 ppm/°C) and currents (<�400 ppm/°C) in standard complementary metal oxide semiconductor (CMOS) processes over wide temperature spans (-55°C to þ163°C). The method involves combining devices with the same polarity (e.g. n-channel MOSFETs in p-well processes and vice versa) in a judicious manner suggested by theory, which side-steps the need for disparate elements such as resistors, diodes, and bipolar transistors, whose thermal variations are more difficult to model and offset mutually; the more so, the wider the temperature range. The close agreement between analysis and simulations (BSIM4) is illustrated by representative circuit design examples embodying the proposed principles. The concepts set forth offer advantages as generally accrue from design simplification and reduced circuit complexity; they are scalable as industrial silicon CMOS processeswhich are not optimised for extended thermal operation-evolve below 50 nm, and suitable to other technologies which find applications in the automotive, aviation, aerospace, energy, and geophysical sensing sectors, among others, such as silicon carbide, wherein MOSFETs can operate above 300°C. Et ignem regunt numeri (Plato) [1]. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.