Thermal test effect on fan-out wafer level package strength

Xu, C.; Zhong, Zhang; Choi, Won Kyung

doi:10.1109/impact.2017.8255915

Cited by 5 publications

(4 citation statements)

References 20 publications

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“…We hypothesize that the increase in the package strength is related to the thermal process, and the epoxy molding compound (EMC) property is affected by the thermal process. The experiment results show that the EMC strength and hardness continuously increase with the increase in the thermal process period (Xu et al, 2017b(Xu et al, , 2017d. The EMC strength may become stable after the 1,000 hours' hightemperature storage test (Xu et al, 2017d).…”

Section: Introductionmentioning

confidence: 93%

“…The experiment results show that the EMC strength and hardness continuously increase with the increase in the thermal process period (Xu et al, 2017b(Xu et al, , 2017d. The EMC strength may become stable after the 1,000 hours' hightemperature storage test (Xu et al, 2017d). The reason is the high temperature increases the EMC glass transition, and the increased glass transition leads to the EMC flexural modulus increase (Mengel et al, 2004;Zhang et al, 2016).…”

Section: Introductionmentioning

confidence: 97%

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Evaluation of fan-out wafer level package strength

Zhong

Choi

2019

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Purpose The fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack. Design/methodology/approach This paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point. Findings The results show that the backside protection tape does not have the ability to enhance the FOWLP strength, and the strength of over-molded structure FOWLP is superior to that of other structure FOWLPs with the same thickness level. Originality/value There is ample research about the silicon strength and silicon die strength. However, there is little research about the package level strength and no research about the FOWLP strength. The FOWLP is made up of various materials. The effect of individual component and external environment on the FOWLP strength is uncertain. Therefore, the study of strength behavior of FOWLP is significant.

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Section: Introductionmentioning

confidence: 93%

Section: Introductionmentioning

confidence: 97%

Evaluation of fan-out wafer level package strength

Zhong

Choi

2019

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“…To make a thin FOWLP (Xu et al, 2017b) with an overmolded (Xu et al, 2017a) structure, the Si chip had to be thinned by grinding. The effects of the thinning processes on the surface finish and the flexural strength of the FOWLPs were studied by measuring the roughness heights of the ground specimens and performing 3PB testing with the specimens placed on a fixture (Xu et al, 2016) on a universal tester.…”

Section: Investigated the Strengths Of Thin Fowlpsmentioning

confidence: 99%

Recent advances and applications of abrasive processes for microelectronics fabrications

Zhong

2019

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Purpose This paper aims to review recent advances and applications of abrasive processes for microelectronics fabrications. Design/methodology/approach More than 80 patents and journal and conference articles published recently are reviewed. The topics covered are chemical mechanical polishing (CMP) for semiconductor devices, key/additional process conditions for CMP, and polishing and grinding for microelectronics fabrications and fan-out wafer level packages (FOWLPs). Findings Many reviewed articles reported advanced CMP for semiconductor device fabrications and innovative research studies on CMP slurry and abrasives. The surface finish, sub-surface damage and the strength of wafers are important issues. The defects on wafer surfaces induced by grinding/polishing would affect the stability of diced ultra-thin chips. Fracture strengths of wafers are dependent on the damage structure induced during dicing or grinding. Different thinning processes can reduce or enhance the fracture strength of wafers. In the FOWLP technology, grinding or CMP is conducted at several key steps. Challenges come from back-grinding and the wafer warpage. As the Si chips of the over-molded FOWLPs are very thin, wafer grinding becomes critical. The strength of the FOWLPs is significantly affected by grinding. Originality/value This paper attempts to provide an introduction to recent developments and the trends in abrasive processes for microelectronics manufacturing. With the references provided, readers may explore more deeply by reading the original articles. Original suggestions for future research work are also provided.

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“…The silicon die must be thin so as to build a thin over-molded [13] structure fan-out wafer-level package [14]. The fan-out wafer-level package also shows better thermal-mechanical reliability performance [15,16] than other packages such as plastic ball grid array packages [17].…”

Section: Introductionmentioning

confidence: 99%

A Study of the Intermetallic Compound Growth in Flip-Chip Packages under Thermal Loading

Chen¹,

Zhong²,

Choi³

2019

J. Mater. Appl.

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The intermetallic compound layers in solder bumps have the brittle feature and can easily fracture under thermal or mechanical loading. Therefore, the intermetallic compound is an issue for the fracture reliability of the solder bumps. In this work, the intermetallic compound growth before and after high temperature storage tests was investigated. The experiment results revealed that the solder bumps with nickel layers could reduce the intermetallic compound growth rate. The nickel layer, which was added in between Cu and SnAg for top solder bumps, was an important factor controlling the intermetallic compound thickness. It was hard to tell the intermetallic compound thickness at time zero; at the time of 147 hours, the intermetallic compound grew to 3.25 µm; at the time of 294 hours, the intermetallic compound grew to 5.25 µm. However, the solder joints were still in good condition.

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Thermal test effect on fan-out wafer level package strength

Cited by 5 publications

References 20 publications

Evaluation of fan-out wafer level package strength

Evaluation of fan-out wafer level package strength

Recent advances and applications of abrasive processes for microelectronics fabrications

A Study of the Intermetallic Compound Growth in Flip-Chip Packages under Thermal Loading

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