Thermally Assisted Superconductor Transistors for Josephson-CMOS Hybrid Memories

Abstract

We have studied on thermally assisted nano-structured transistors made of superconductor ultra-thin films. These transistors potentially work as interface devices for Josephson-CMOS (complementary metal oxide semiconductor) hybrid memory systems, because they can generate a high output voltage of sub-V enough to drive a CMOS transistor. In addition, our superconductor transistors are formed with very fine lines down to several tens of nm in widths, leading to very small foot print enabling us to make large capacity hybrid memories. Our superconductor transistors are made with niobium titanium nitride (NbTiN) thin films deposited on thermally-oxidized silicon substrates, on which other superconductor circuits or semiconductor circuits can be formed. The NbTiN thickness dependence of the critical temperature and of resistivity suggest thermally activated vortex or anti-vortex behavior in pseudo-two-dimensional superconducting films plays an important role for the operating principle of the transistors. To show the potential that the transistors can drive MOS transistors, we analyzed the driving ability of the superconductor transistors with HSPICE simulation. We also showed the turn-on behavior of a MOS transistor used for readout of a CMOS memory cell experimentally. These results showed the high potential of superconductor transistors for Josephson-CMOS hybrid memories.

Multilayered Heater Nanocryotron: A Superconducting-Nanowire-Based Thermal Switch

“…There are several applications where introduction of the hTron offers the possibility of performance benefits over traditional techniques involving Josephson junctions and other types of superconducting switches. The hTron offers several advantages including high gain, no leakage current between the gate and channel, the ability to drive high-impedance loads, the possibility of large fan-out, and robustness to magnetic fields [1][2][3][4][5]. These properties make hTron devices an excellent choice that can provide the necessary on-chip platform to interface superconducting circuits involving superconducting single-flux quantum (SFQ) electronics to room-temperature control systems.…”

“…The electron heat capacity is estimated as C e,Ti (T e,Ti ) = γ Ti T e,Ti , with γ Ti = 320 J/m 3 K 2 [19]. The titanium phonon system is treated using the Debye model with C ph,Ti (T ph,Ti ) = α Ti T 3 ph,Ti , in which α Ti = 2.47 J/m 3 K 4 [19]. The Ti phonon thermal conductivity is estimated as κ ph,Ti = α Ti D ph,Ti T 3 ph,Ti , with the phonon diffusion coefficient D ph,Ti ∼ 0.27 cm 2 /s, which represents the Casimir limit.…”

“…The titanium phonon system is treated using the Debye model with C ph,Ti (T ph,Ti ) = α Ti T 3 ph,Ti , in which α Ti = 2.47 J/m 3 K 4 [19]. The Ti phonon thermal conductivity is estimated as κ ph,Ti = α Ti D ph,Ti T 3 ph,Ti , with the phonon diffusion coefficient D ph,Ti ∼ 0.27 cm 2 /s, which represents the Casimir limit. The electron-phonon coupling constant is e-ph,Ti = 1.3 × 10 9 W/m 3 K 5 [20].…”

“…In recent years, there have been many attempts to develop electrothermal superconducting switches based on the destruction of superconductivity in a current-carrying nanowire, which leads to an impedance change to drive a load. One of these approaches uses a superconducting three-terminal device called a nanocryotron (nTron) [1][2][3][4]. In an nTron, a narrow nanowire, known as the gate, is connected to a wider superconducting nanowire, termed the channel, through a small constriction.…”