Thermally-aware composite run-time CPU power models

Abstract

Abstract-Accurate and stable CPU power modelling is fundamental in modern system-on-chips (SoCs) for two main reasons: 1) they enable significant online energy savings by providing a run-time manager with reliable power consumption data for controlling CPU energy-saving techniques; 2) they can be used as accurate and trusted reference models for system design and exploration. We begin by showing the limitations in typical performance monitoring counter (PMC) based power modelling approaches and illustrate how an improved model formulation results in a more stable model that efficiently captures relationships between the input variables and the power consumption. Using this as a solid foundation, we present a methodology for adding thermal-awareness and analytically decomposing the power into its constituting parts. We develop and validate our methodology using data recorded from a quad-core ARM Cortex-A15 mobile CPU and we achieve an average prediction error of 3.7% across 39 diverse workloads, 8 Dynamic Voltage-Frequency Scaling (DVFS) levels and with a CPU temperature ranging from 31• C to 91• C. Moreover, we measure the effect of switching cores offline and decompose the existing power model to estimate the static power of each CPU and L2 cache, the dynamic power due to constant background (BG) switching, and the dynamic power caused by the activity of each CPU individually. Finally, we provide our model equations and software tools for implementing in a run-time manager or for using with an architectural simulator, such as gem5. I. INTRODUCTIONWhile mobile devices are required to be ever-more energy efficient, mobile CPU designs are becoming more complex in order to achieve the ever-increasing performance demand of new applications. Key to saving energy is the system's runtime manager (RTM), which controls CPU energy-saving techniques (such as dynamic voltage frequency scaling [DVFS] or heterogeneous cores [e.g. ARM's big.LITTLE technology]) in order to trade off power and performance based on the current conditions and requirements. However, in order to make these trade-offs effectively, run-time knowledge of how power is being consumed is essential. A fast and accurate power model, that is able to predict the current power consumption at runtime, can therefore be used with a run-time manager to make significant energy savings [1].Previously, top-down regression-based models using performance monitoring counters (PMCs) as inputs have been widely shown to be effective in estimating CPU power [2]- [13]. Topdown approaches use power measurements from real devices and predict this measured power using metrics. Therefore they

Thermal aware task assignment for multicore processors using genetic algorithm

“…However, the static power is dissipated because of leakage current through reverse biased junctions of the transistor [19]. The dynamic power dissipation (Pd) can be expressed (3) [20],…”

Hardware-Validated CPU Performance and Energy Modelling

“…A MAPE of 5.6% was achieved, larger than the quoted 2.8%. However, there are several potential reasons for this: the board is not identical and components such as the SoC, power sensors and voltage regulators are subject to variation; the model can be affected by differences in storage media (the read write speeds of the SD card/eMMC); and the ambient temperature conditions have a large effect on power [25]. The coefficients were re-tuned using the same PMC selection from [8] and the data collected from the HW platform.…”

Empirical CPU power modelling and estimation in the gem5 simulator

“…Such power models are built from PMC data and measured power consumption from a CPU/SoC [17], [18]. Many CPUs have PMCs which count certain architectural and microarchitectural events, such as L2 cache misses, an instruction speculatively executed.…”