Thermoelastic model of dislocations in wafers

Thermal Conditions in Rapid Thermal Processing System Using Circular Infrared Lamp

“…It is noted here that the rays from the tungsten/halogen filament lamps heat a mirror polished silicon substrate surface surrounded by reflectors. Since extremely complicated paths of the rays emitted from the tungsten/ halogen filament lamps must be taken into account, the application of the usual theoretical models 8,10,19,[21][22][23][24][25][26][27][28][29][30] to the RTP system is considered to be difficult. This has been the catalyst for development of the direct approach ray trace simulation model (DARTS), 31 which is an application of the ray tracing method.…”

A Direct Approach for Evaluating the Thermal Condition of a Silicon Substrate under Infrared Rays and Specular Reflectors

“…For this purpose, many researchers have studied models for evaluating the temperatures of the silicon substrates in the furnaces for oxidation and diffusion by accounting for the diffusive reflectors, infrared radiation heat, and the reflections between the walls of the furnace and the substrates. 7,9,12,[27][28][29][30][31][32] However, very few models which take into account the three-dimensional configuration of the RTP system using reflectors, tungsten/halogen filament lamps, and a silicon substrate have been discussed, 26 because of the difficulty in accounting for the view factor under the complicated reflections of the rays in the RTP system. 7 Although an image source of the lamp has been used to account for the rays reflected at the surface of the specular reflector near the real source of the lamp, the image construction is not practical in three-dimensional systems.…”

Threshold Voltage Instability Due to Oxygen Thermal Donor Impurities in Metal Oxide Semiconductor Field Effect Transistors

“…Mokuya et al investigated the temperature distributions in regularly spaced wafers in a row in a furnace tube theoretically and experimentally, and showed that the temperature gradient in a wafer becomes larger from the bottom position (Y ϭ 0) to the top position S0013-4651(99)05-089-2 CCC: $7.00 © The Electrochemical Society, Inc. and the distribution was different according to the wafer set position on the boat. [34][35][36] This indicates that the thermal stress which is nearly proportional to the temperature gradient 37 becomes higher near the top position of wafer, i.e., near the orientation flat in the present work. The stress induced in the Si substrate enhances the generation of point defects (interstitial and vacancy).…”