Thin Body III–V-Semiconductor-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors on Si Fabricated Using Direct Wafer Bonding

Abstract

We have demonstrated thin body III-V-semiconductor-on-insulator (III-V-OI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) on a Si wafer fabricated using a novel direct wafer bonding (DWB) process. A 100-nm-thick InGaAs channel was successfully transferred by the low damage and low temperature DWB process using low energy electron cyclotron resonance (ECR) plasma. The transferred InGaAs-OI nMOSFET on the Si wafer exhibited a high electron channel mobility of 1200 cm 2 ÁV À1 Ás À1 , indicating that the present DWB process allows us to form thin III-V-OI channels without serious plasma and bonding damage. This technology is expected to open up the possibility of integrating the ultrathin body III-V-OI MOSFETs on Si platform.

Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

“…5), these hetero-buffers provided adequate quality substrates to enable infrastructure development, process integration, and device challenges to be addressed. Further improvements in buffer thickness and quality are required for true VLSI while maintaining the intrinsic properties of the III-V channels [4] Alternative promising III-V on Si technologies include bonding [5], aspect ratio trapping [6], and epitaxial layer overgrowth [7].…”

High mobility channel MOS device technologies toward nano-CMOS era

“…We have employed the direct wafer bonding (DWB) process of InGaAs/InP wafers with Si substrates for fabricating the [no53Gao47As-on-[nsulator substrates [7][8][9][10][11][12][13][14][15]. ECR-plasma SiOz [7,8,11,14] and ALD Ab03 films [9][10][11][12][13]15] have been used as buried-oxide (BOX) layers.…”

III–V nanocrystal formation in ion-implanted Ge and Si via liquid phase epitaxy during short-time flash lamp annealing

“…Besides the lattice mismatch, the difference in thermal expansion coefficients is also detrimental when processing steps at elevated temperatures need to be performed. However, integration of III-V's has been achieved by several techniques, like molecular beam epitaxy (MBE) [10] or wafer bonding [11,12]. While the integration of III-V's in Si has already been studied to some extent over the last years, direct integration into Ge is still sparsely found [13].…”