Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation

Abstract

Gate-oxide breakdown is a key mechanism limiting IC lifetime. Lifetime is typically extrapolated from accelerated tests on test capacitors, but estimating product reliability from such results requires making a number of often-untested assumptions. This paper details a capacitor-based model and compares the predictions of the model to results from accelerated lifetest of actual logic CPU products, discussing the assumptions which make such a comparison necessary. For the technology studied, lifetest failure rate was somewhat lower than model prediction, and failure analysis indicated that important factors included the different sensitivities of logic circuits versus cache cells and of n and p transistors in the cache. Analysis of the factors involved in determining oxide-breakdown reliability and of the statistical uncertainties in capacitor-based models indicates that it is important to calibrate models to product data, including these effects. Once a model is validated, this paper discusses how it can be used to assess the reliability impact of changes in silicon processing and product use conditions. Index Terms-CPU, failure rate, lifetest, time-dependent dielectric breakdown (TDDB), V CCMIN .

On the degradation of OTA-C--based CMOS low-power filter circuits for biomedical instrumentation

“…Biomedical device failure or the disorder of biomedical device function during diagnosis and treatment processes may have extremely negative effects. Thus, in order to determine the ultimate performance, the reliability must be modeled for specific operating condition [1][2][3][4][5][6][7][8][9][10][11][12][13].…”