Thirty years of lithography simulation

Mack, Chris A.

doi:10.1117/12.601590

Cited by 36 publications

(18 citation statements)

References 43 publications

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“…Increasingly sophisticated "first principles" models have been developed to describe the physics and chemistry of these processes, with the result that critical dimensions and 3D profiles now can be accurately predicted for a variety of processes through a broad range of process variations. 12 (These models certainly do include multiple approximations and simplifications, and are not truly atomic or molecular level representations, though interesting work has more recently been conducted in the arena of stochastic modeling models [13][14][15] ). The quasirigorous mechanistic nature of TCAD models, applied in three dimensions, implies an extremely high computational load.…”

Section: Introductionmentioning

confidence: 99%

Challenges for patterning process models applied to large scale

Sturtevant

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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Full-chip patterning simulation has been utilized in semiconductor manufacturing for more than ten years, and has been a key enabler for multiple technology generations, from 130 nm to the emerging 14 nm node. This span has featured two wavelength changes, a progression of optical NA increases (and a subsequent decrease), and a variety of patterning processes and chemistries. Full-chip patterning simulations utilize quasirigorous optical models and semiempirical resist and etch process models. There has been steady improvement in the predictive power and computational efficiency of the patterning models used in full chip simulation tools, and this paper will review this progress as well as the factors that ultimately limit the predictive capability of such models. In addition, this paper will outline the new process simulation challenges that are emerging as the industry approaches sub-0.25 k1 patterning. These challenges lie principally in improving accuracy and predictive capability, including 3D effects, for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

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Section: Introductionmentioning

confidence: 99%

Challenges for patterning process models applied to large scale

Sturtevant

2012

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

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“…As industry pioneer and PROLITH founder Chris Mack has described [6][7] , lithography simulation has allowed engineers to perform virtual experiments not easily realizable in the fab, it has enabled cost reduction through narrowing of process options, and has been used to troubleshoot problems encountered in manufacturing. A less tangible but nonetheless invaluable benefit has been the development of "lithographic intuition", and fundamental system understanding for photoresist chemists, lithography researchers, and process development engineers.…”

Section: Introductionmentioning

confidence: 99%

The evolution of patterning process models in computational lithography

Sturtevant

2010

SPIE Proceedings

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Thirty five years have passed since the first lithography process models were presented, and since that time there has been remarkable progress in the predictive power, performance, and applicability of these models in addressing many different challenges within the semiconductor industry. The impact has been profound, and this paper will attempt to highlight some of the key contributions which have been made, particularly as patterning simulation has moved beyond the realm of process development to full chip production enablement. In addition, this paper will outline the new process simulation challenges which emerge as the industry approaches sub-0.25 k 1 patterning. These challenges lie principally in driving towards ever improved accuracy for an expanding set of processes and failure modes, while maintaining or improving full chip data preparation cycle times.

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“…As a result, OPC is sometimes referred to as optical process correction since, in reality, corrections are based on the entire process rather than just the optical proximity effects. This empirical technique results in a "lumped" set of rules or a physical model which includes the photomask manufacturing process effects, as well as the optics of the wafer exposure, and the chemistry of the develop and bake processes and sometimes the wafer etch processes 3 . Without knowledge of the photomask manufacturing process capabilities, the designed corrections can sometimes generate patterns which are difficult, if not impossible, to resolve on the photomask.…”

Section: Introductionmentioning

confidence: 99%

Implications of wafer design for manufacturing practices on photomask manufacturing

Watts¹,

Rankin²,

Magg³

2005

SPIE Proceedings

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Focus on Design for Manufacturing (DFM) in semiconductor device design has increased as semiconductor manufacturing technology has become more complex. Many of the techniques developed to improve wafer yield and manufacturability can also be applied to the photomask manufacturing process. For example, for the last several technology nodes, semiconductor manufacturers have known that pattern density and uniformity can have significant impact on wafer processes such as etching and chemical mechanical polishing. Photomask manufacturing can also be impacted by pattern density and its uniformity.Some of these DFM practices can be beneficial if applied directly to photomask manufacturing while some of them can make photomask manufacturing significantly more difficult. Optical proximity correction (OPC), which involves convoluting the design shape to account for optical, physical and chemical processes, is increasingly required to support advanced lithography; some of the operational parameters of the OPC, such as the fragmentation run length, challenge mask resolution capability, image fidelity, defect inspection, mask repair, and dimensional metrology of photomasks. Sub-resolution assist features (SRAFs), which are utilized to create robust wafer lithography are often the most challenging mask features to create. The size and placement of SRAFs on photomasks are factors that impact photomask manufacturability in terms of image resolution, inspection, and dispositioning criteria. As OPC and other DFM processes become more widely deployed in an effort to make robust wafer manufacturing processes, the photomask maker needs to be involved to evaluate the implications to photomask manufacturing and assist in optimizing these DFM procedures to maximally benefit both the photomask and semiconductor manufacturing processes.

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Thirty years of lithography simulation

Cited by 36 publications

References 43 publications

Challenges for patterning process models applied to large scale

Challenges for patterning process models applied to large scale

The evolution of patterning process models in computational lithography

Implications of wafer design for manufacturing practices on photomask manufacturing

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