2023 IEEE International Symposium on Circuits and Systems (ISCAS) 2023
DOI: 10.1109/iscas46773.2023.10182204
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THRAM: A Template-based Heterogeneous CGRA Modeling Framework Supporting Fast DSE

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Cited by 7 publications
(1 citation statement)
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“…Although the coarse-grained reconfigurable processor's software and hardware design space is board, there are several common features, including relatively simple functional units, reconfigurable on-chip networks and low-level software APIs. In this section, we describe an early version of CGRA architecture model generated by the compiler TRAM, as shown in Figure 1 [12,15].…”
Section: Target Cgra Processormentioning
confidence: 99%
“…Although the coarse-grained reconfigurable processor's software and hardware design space is board, there are several common features, including relatively simple functional units, reconfigurable on-chip networks and low-level software APIs. In this section, we describe an early version of CGRA architecture model generated by the compiler TRAM, as shown in Figure 1 [12,15].…”
Section: Target Cgra Processormentioning
confidence: 99%