Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors

Abstract

We provide an analysis of thread-management techniques that increase performance or reduce energy in multicore and Simultaneous Multithreaded (SMT) cores. Thread delaying reduces energy consumption by running the core containing the critical thread at maximum frequency while scaling down the frequency and voltage of the cores containing noncritical threads. In this article, we provide an insightful breakdown of thread delaying on a simulated multi-core microprocessor. Thread balancing improves overall performance by giving higher priority to the critical thread in the issue queue of an SMT core. We provide a detailed breakdown of performance results for thread-balancing, identifying performance benefits and limitations. For those benchmarks where a performance benefit is not possible, we introduce a novel thread-balancing mechanism on an SMT core that can reduce energy consumption. We have performed a detailed study on an Intel microprocessor simulator running parallel applications. Thread delaying can reduce energy consumption by 4% to 44% with negligible performance loss. Thread balancing can increase performance by 20% or can reduce energy consumption by 23%.

Energy-Efficient Compilation of Irregular Task-Parallel Loops

“…The work-load of input independent parts is calculated through static analysis, and combined with the work-load of input dependent parts, computed at runtime to find the work-load of each task. • Considering the continuously decreasing work-loads of the tasks (all not at the same rate), we propose an algorithm to compute the remaining work-loads and perform frequencyscaling at regular intervals based on these remaining work-loads (instead of the initial estimated work-load (Ozturk et al 2013) or the work-done so far (Rakvic et al 2010;Cai et al 2008;Chen et al 2014)). • Considering the special nature of the MSMC systems, especially in the context of ITP programs, we propose an algorithm that performs thread-migration at different intervals to maximize the load-imbalance among the sockets, which in turn improves the opportunities for frequency-scaling.…”

“…Our technique uses a user-specified parameter (wtTmP) to fine-tune the frequencies of the non-critical-sockets, so the percentage increase in the execution time of the critical-thread is bounded by wtTmP. • We have implemented X10Ergy in the x10-v-2.4 compiler and evaluated it against the Baseline versions (with -NO_CHECKS flag) and two prior works: the meeting-points based optimization (MP-OPT) of Rakvic et al (2010) and the work-load-aware optimization (EEWA-OPT) of Chen et al (2014). We show that on average, on IMSuite benchmarks (i) compared to Baseline, X10Ergy reduces the energy consumption by 15% with 2% increase in execution time.…”

“…This scheme does not lead to much benefits either as there is not much socket-level load-imbalance. Further Cai et al (2008) and Rakvic et al (2010) show that even in the presence of some load-imbalance, this simple scheme is not much beneficial. Thus, we see that in the context of MSMC systems, there is less scope to reduce the frequency of the non-critical-sockets, using MSMC-oblivious schemes.…”

“…Thus, instead of balancing the work-load, many prior approaches (Liu et al 2005;Rakvic et al 2010;Cai et al 2008;Ozturk et al 2013;Chen et al 2014;Rauber and Rünger 2015) reduce the energy consumption by reducing the frequency of the cores on which the non-criticalthreads are mapped such that all the threads reach the join-point at the same time, thereby reducing the energy consumption without any increase in the execution time. Many of these schemes (Liu et al 2005;Rakvic et al 2010;Cai et al 2008;Chen et al 2014;Rauber and Rünger 2015) assume that the frequency of each core can change independently, which is not true in case of MSMC systems. We can extend these schemes to MSMC systems by assuming that the work-load of the socket is equal to that of the thread executing the task with maximum work-load on that socket, and using the respective schemes to reduce frequencies of the "non-critical"-sockets (sockets not running the critical-thread)-we call such an extension as MSMC-oblivious scheme.…”

Making the Most of SMT in HPC

“…Rakvic et al [2010] aim to improve performance and energy consumption of parallel workloads by identifying critical threads in a parallel region to use SMT to give higher priority to the critical thread for thread balancing. These techniques are complementary to ours.…”