Threats and Challenges in Reconfigurable Hardware Security

Kastner, Ryan; Huffmire, Ted

doi:10.21236/ada511928

Cited by 7 publications

(4 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For instance, in contrast to FPGAs, the attacker in the case of microprocessors, can focus on certain components of the processor because of the knowledge about the program execution and design structure [56]. This is also demonstrated in [8], where King et al have found that a microprocessor can be hacked to gain high-level access with only a small hardware circuit, which could contain thousand logic gates.…”

Section: Reconfigurable Computing Has a Different Structural Design Thanmentioning

confidence: 99%

Hardware Trojans in Reconfigurable Computing

Ahmed

2021

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)

View full text Add to dashboard Cite

Inestimable appreciation and earnest gratitude for the help and support are extended to many remarkable people who have been around me throughout this journey and without whom the accomplishment of this thesis would not have been possible. I would like to meekly express my thanks to all my colleagues, friends, family, and specifically to those mentioned in the following lines.First and foremost, I would like to express my deepest thanks to my supervisor, Prof. Dr. Marco Platzner, for his invaluable guidance, persistent help, and immeasurable support throughout this research. He has always been kind and his generosity, dynamism, sincerity, scholarly advice, and professional attitude have deeply inspired, motivated and helped me to a great extent to complete this thesis. It was a great privilege and honor to work under his supervision where I have learnt a lot from his experience, skills, and leadership. Furthermore, I would like to thank him and Prof. Dr. Sybille Hellebrand for devoting their time and effort to review this thesis, together with all the committee members for evaluating my research.I am sincerely grateful to the people of the CEG for providing such a pleasant and professional working environment during my stay. A special thanks goes to my colleague cum mentor Tobias Wiersema who has been there all the time for scientific discussions in a very professional way and also his help regarding social matters in Germany is highly regarded.Besides, many thanks also goes to

show abstract

Section: Reconfigurable Computing Has a Different Structural Design Thanmentioning

confidence: 99%

Hardware Trojans in Reconfigurable Computing

Ahmed

2021

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)

View full text Add to dashboard Cite

show abstract

“…In this section we review approaches to reconfigurable hardware security, an area that has gained interest only recently. An overview of security risks present in every step of the life cycle of reconfigurable hardware is presented by Kastner and Huffmire [2]. Drimer [4] also provides an exhaustive survey of possible attacks, involved parties, stages of life cycles, and possible defenses.…”

Section: Related Workmentioning

confidence: 99%

“…As a first application of PCH, we focus on runtime combinational equivalence checking (CEC) in this paper. Runtime CEC enables a consumer International Journal of Reconfigurable Computing to verify that a requested reconfigurable module actually adheres to its functional specification and, thus, eliminates a major security risk according to [2].…”

Section: Introductionmentioning

confidence: 99%

Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification

Drzevitzky

Kastens

Platzner

2010

International Journal of Reconfigurable Computing

View full text Add to dashboard Cite

Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, we elaborate on the presentation of proof carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes a key concept from software security, known as proof-carrying code, into the reconfigurable hardware domain. We outline the PCH concept and discuss runtime combinational equivalence checking as a first online verification problem applying the concept. We present a prototype tool flow and experimental results demonstrating the feasibility and potential of the PCH approach.

show abstract

“…However, the PR design flow can expose FPGAs to security risks [McLean and Moore 2007;Kastner and Huffmire 2008;Huffmire et al 2008]. Unlike traditional software where resources are managed by an operating system, IP cores necessarily have very fine-grain control over the underlying hardware.…”

Section: Introductionmentioning

confidence: 99%

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

Kȩpa

Morgan

Kosciuszkiewicz

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

The growth of the Reconfigurable Computing (RC) systems community exposes diverse requirements with regard to functionality of Electronic Design Automation (EDA) tools. Low-level design tools are increasingly required for RC bitstream debugging and IP core design assurance, particularly in multiparty Partially Reconfigurable (PR) designs. While tools for low-level analysis of design netlists do exist, there is increasing demand for automated and customisable bitstream analysis tools.This article discusses the need for low-level IP core verification within PR-enabled FPGA systems and reports FDAT (FPGA Design Analysis Tool), a versatile, modular and open tools framework for low-level analysis and verification of FPGA designs. FDAT provides a set of high-level Application Programming Interfaces (APIs) abstracting the Xilinx FPGA fabric, the implemented design (e.g., placed and routed netlist) and the related bitstream. A lightweight graphic frontend allows custom visualisation of the design within the FPGA fabric. The operation of FDAT is governed by "recipe" scripts which support rapid prototyping of the abstract algorithms for system-level design verification. FDAT recipes, being Python scripts, can be ported to embedded FPGA systems, for example, the previously reported Secure Reconfiguration Controller (SeReCon) which enforces an IP core spatial isolation policy in order to provide run-time protection to the PR system.The paper illustrates the application of FDAT for bit-pattern analysis of Virtex-II Pro and Virtex-5 inter-tile routing and verification of the spatial isolation between designs.

show abstract

Threats and Challenges in Reconfigurable Hardware Security

Cited by 7 publications

References 19 publications

Hardware Trojans in Reconfigurable Computing

Hardware Trojans in Reconfigurable Computing

Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

Contact Info

Product

Resources

About