Three‐Dimensional (3D) Integration

McMahon, Jeffrey M.; Lu, Jian‐Qiang; Gutmann, R.J.

doi:10.1002/9780470180907.ch15

Cited by 2 publications

(1 citation statement)

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“…Figure 3 shows defects in a region where post-CMP topography is too big to be accommodated. Voids are visible in the BCB-BCB interfaces near the copper structure where post-CMP topography is expected due to dielectric loss [18,19]. An area with a visible scratch is shown in Figure 3 to illustrate that voiding can be produced in areas where no copper structure exists.…”

Section: Observation Of Bonding Interfacesmentioning

confidence: 95%

Bonding interfaces in wafer-level metal/adhesive bonded 3D integration

McMahon

Chan

Lee

et al. 2008

2008 58th Electronic Components and Technology Conference

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This paper examines the bonding interfaces in a back-endof-line (BEOL) compatible wafer-level three-dimensional (3D) integrated circuit (IC) technology platform with wafer bonding of damascene patterned metal/adhesive surfaces. Copper and partially cured benzocyclobutene (BCB) are selected as the metal and adhesive, respectively. To prevent bonding voids and defects, the Cu-Ta-BCB, Cu-Cu, and BCB-BCB interfaces are investigated. Bonding voids and defects at the Cu-Ta-BCB and Cu-Cu interfaces are attributed to surface defects, topography, and thermomechanical stress resulting in plastic deformation of the copper during bonding. Defects observed at the BCB-BCB interface are attributed to an inability to accommodate large post-CMP topography. Short-loop wafer bonding experiments are performed using a process that eliminates the Cu/Ta interconnect structure, but provides the capability to produce controlled topography. Key parameters to prevent void formation at the BCB-BCB interface are the topography depth and pitch, as well as the BCB cure, denoted here as the crosslinking percentage. For BCB-BCB bonds formed with a partial-cure preparation of ~70-90% crosslinking, features ~1 µm in pitch are accommodated when the depth of the BCB topography is less than 12 nm. The accommodation depth is increased by a factor of ~4 with 50% crosslinked BCB. IntroductionThe 3D integration technology platform with wafer bonding of damascene patterned metal/adhesive redistribution layers [1,2] would provide the capability for high-density inter-wafer interconnect and could produce well-bonded BCB-BCB and Cu-Cu interfaces in one unit process step. After a single-level damascene patterned Cu/BCB layer is added to fully fabricated IC wafers, the patterned surfaces are forced together at elevated temperature to promote bonding of the BCB-BCB and Cu-Cu interfaces. This 3D platform enables heterogeneous integration with a high density of low inductance inter-wafer interconnects.After bonding, a typical process flow employs top-side wafer thinning to a stop layer. Stop layer approaches include chemically inert layers such as buried oxide (BOX) in silicon on insulator (SOI), or patterned layers such as via-first isolated trenches. If a chemical etch stop is utilized, then through-silicon via (TSV) formation follows thinning. In either stop layer approach, the density of interconnect at the top of the stack will be limited by the TSV density, which is expected to be lower than that of the bonded Cu-Cu interwafer interconnect.The process can be repeated to allow addition of more functional layers to the top of the stack after TSV processing. Such addition is possible using a number of approaches, but

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Section: Observation Of Bonding Interfacesmentioning

confidence: 95%