Three dimensional dynamic random access memory

Kirihata, T.

doi:10.1109/ltb-3d.2014.6886142

Cited by 3 publications

(2 citation statements)

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“…With the development of innovative memories, emerging memory technologies such as non-volatile memory [1], [2], 3D-stacked [3], [4], memory have been integrated into the memory system, thus effectively complemented traditional DRAM. For example, the Intel Knight Landing (KNL) processor [5] incorporates high bandwidth memory (HBM) into the processor, which achieves much higher bandwidth than DRAM when the application exhibits high parallelism and sequential access.…”

Section: Introductionmentioning

confidence: 99%

ADSM: Adaptive Data Scheduling Method for Hybrid Memories in Distributed System

Sun

Yang

et al. 2019

IEEE Access

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With the deployment of innovative memories such as non-volatile memory and 3D-stacked memory in distributed systems, how to improve the application performance by utilizing the unique characteristics of these hybrid memories remains an active research direction. For instance, the Intel Knight Landing (KNL) processor incorporates a High Bandwidth Memory (HBM) using 3D-stacked technology with traditional DRAM onto the same chip. HBM achieves much higher bandwidth than traditional DRAM when the application exhibits high parallelism and sequential access. In this paper, we propose a new metric SP-factor to guide the data scheduling in distributed system using hybrid memories such as HBM and DRAM. The SP-factor incorporates the data access patterns including data block size and data access parallelism, which leads to better data scheduling decision for higher performance. We apply SP-factor to several data eviction policies on the hybrid memory system, which achieves better performance. Moreover, an adaptive data scheduling method (ADSM) is proposed for such hybrid memory system with HBM and DRAM. ADSM can dynamically adjust scheduling decisions based on runtime performance metrics so that it can adapt to workloads with different data access patterns. Our experimental results show that ADSM can significantly improve the performance of the representative workloads. For SQL query application with mixed access pattern, the cache hit ratio increases by 10.4% and the execution time reduces by 14.6% using ADSM compared to ARC policy.

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Section: Introductionmentioning

confidence: 99%

ADSM: Adaptive Data Scheduling Method for Hybrid Memories in Distributed System

Sun

Yang

et al. 2019

IEEE Access

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“…1 illustrates a high-performance system based on 3DI technologies, where the two key elements are: a high-performance micro-processor (µP) chip stacked over a high-density cache memory, and the high-density lowpower DRAM stacks supporting the µP. [5] Two early prototypes [6,7], were developed to demonstrate 3D cache feasibility and evaluate TSV processing [8] by stacking two embedded DRAM (eDRAM) chips. Compared with chip-tochip 3DI, wafer-scale 3DI offers a high-volume low-cost production solution to achieve these benefits.…”

Section: Introductionmentioning

confidence: 99%

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Lin

Faltermeier

Winstel

et al. 2014

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

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