Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic

Nedjah, Nadia; Mourelle, Luiza Macedo

doi:10.1109/tcsi.2005.858767

Cited by 38 publications

(27 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The square and multiply step can be performed either in parallel [22] or sequentially [13]. Booth encoding is also used to increase the number of "00"-combinations of exponent bits in simultaneous exponentiation [18].…”

Section: Related Workmentioning

confidence: 99%

“…Nedja and Mourelle [22] have shown that for operands larger than 512 bit, the systolic array implementation improves the time × area product over other implementations. They compared their work with that of Blum and Paar [5], which was one of the first milestones for systolic array implementations.…”

Section: Related Workmentioning

confidence: 99%

“…They compared their work with that of Blum and Paar [5], which was one of the first milestones for systolic array implementations. Systolic array Montgomery multipliers have been implemented in 2-dimensional [22,21] and 1-dimensional designs [24]. The 1-dimensional variant requires less silicon to implement, but is slower than the 2-dimensional implementation.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Dedicated Hardware for Attribute-Based Credential Verification

Ottoy

Lapon

Naessens

et al. 2013

Communications and Multimedia Security

View full text Add to dashboard Cite

Abstract. Attribute-based credentials systems offer a privacy-friendly solution to access electronic services. In this field, most research has been directed into optimizing the prover operations and exploring the usability boundaries on mobile platforms like smart cards and mobile phones. This research assumes that the verification of credential proofs occur at a powerful back end. However, a broad range of (embedded) applications lack this powerful back end.This article shows that hardware accelerators for modular exponentiations, greatly reduce the run time of applications that require credential verification in an embedded context. In addition, when verification requires a considerable amount of the total run time (i.e., communication included), the use of dual-base (simultaneous) exponentiation hardware further increases the overall performance.All tests have been performed in a practical setup between a smartphone and an embedded terminal using NFC communication.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Dedicated Hardware for Attribute-Based Credential Verification

Ottoy

Lapon

Naessens

et al. 2013

Communications and Multimedia Security

View full text Add to dashboard Cite

show abstract

“…One of the widely used algorithms for efficient modular multiplication is Montgomery's algorithm [5,8,9],. This algorithm computes the modular product of two integers modulo a third one without performing any trial divisions.…”

Section: The Modular Multipliermentioning

confidence: 99%

High-Performance Hardware of the Sliding-Window Method for Parallel Computation of Modular Exponentiations

Nedjah

Mourelle

2009

Int J Parallel Prog

View full text Add to dashboard Cite

Modular exponentiation is a basic operation in various applications, such as cryptography. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. Therefore, many researchers have devoted special interest to providing smart methods and efficient implementations for modular exponentiation. One of these methods is the sliding-window method, which preprocesses the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel hardware for computing modular exponentiation using the sliding-window method. The partitioning strategy used allows variablelength non-zero partitions, which increases the average number of zero partitions and so decreases that of non-zero partitions. It performs the partitioning process in parallel with the pre-computation step of the exponent so no overhead is introduced. The implementation is efficient when compared against related existing hardware implementations.

show abstract

“…To assess the performance of the proposed method and underlying implementation, we use two different previous implementations of the MM [2,3]. These implementations are based on the Montgomery MM: one is sequential and the other is systolic, which are included here to allow for a self-contained paper.…”

Section: Introductionmentioning

confidence: 99%

Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems

Nedjah

Mourelle

Santana

et al. 2012

IET Comput. Digit. Tech.

Self Cite

View full text Add to dashboard Cite

Most cryptographic systems are based on modular exponentiation (ME). It is performed using successive modular multiplications (MMs). In this case, there are many ways to improve the throughput of a cryptographic system implementation: one is reducing the number of the required MMs and the other is reducing the time spent in performing a single MM and a third way consists of executing required independent modular multiplications (IMMs) in parallel. With the purpose of further accelerating the computation of ME, we investigate the impact of these three strategies. First, we propose a massively parallel scheme aiming at performing all IMMs concurrently. The scheme is based on the m-ary exponentiation method, which groups the exponent bits into partition so that the number of required MMs is reduced, provided that some common modular powers are pre-computed and stored for future repeated use. Finally, two different implementations for the MM are used: one is sequential and the other systolic. This investigation is culminated by a comparison of the speedups yielded against the extra-costs due for seven different implementations. One implementation is software based and the other six are hardware based.

show abstract

Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic

Cited by 38 publications

References 15 publications

Dedicated Hardware for Attribute-Based Credential Verification

Dedicated Hardware for Attribute-Based Credential Verification

High-Performance Hardware of the Sliding-Window Method for Parallel Computation of Modular Exponentiations

Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems

Contact Info

Product

Resources

About