Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 nm Node

Vega-Gonzalez, V.; Bekaert, Joost; Kesters, Els; Le, Quoc Toan; Lorant, Christophe; Teugels, Lieve; Heylen, N.; El-Mekki, Zaid; Veen, M. van der; Webers, Tomas; Wilson, Chris; Vats, H.; Rynders, Luc; Cupak, M.; Uk-Lee, J.; Drissi, Youssef; Halipre, L.; Charley, Anne-Laure; Verdonck, Patrick; Witters, T.; Gompel, S. V.; Briggs, B.; Kimura, Yoshie; Jourdan, N.; Ciofi, Ivan; Gupta, Anshul; Contino, Antonino; Boccardi, G.; Larivière, S.; Dupas, L.; De-Wachter, B.; Vancoille, E.; Decoster, Stefan; Lazzarino, Frédéric; Ercken, Monique; Debacker, Peter; Kim, R.; Trivkovic, Darko; Croes, Kristof; Leray, Philippe; Dillemans, Leander; Chen, Y.-F.; Tőkei, Zsolt; Versluijs, Janko; Leśniewska, A.; Paolillo, Sara; Baert, Rogier; Puliyalil, Harinarayanan

doi:10.1109/iedm19573.2019.8993538

Cited by 13 publications

(4 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A typical film stack of the BEOL metal layer in the 3 nm CFET is shown in Figure 3 [6] . From bottom to top, the film stack consists of a silicon substrate, a 60 nm thick Cobalt (Co), a 60 nm thick low k material (Black Diamond, BD), and a 15 nm thick Titanium Nitride (TiN) as a hard mask.…”

Section: The Dbo Simulation Results In 3 Nm Cfet Beol Metal Layer Fil...mentioning

confidence: 99%

A study of diffraction-based overlay (DBO) on a 3nm CFET metal layer

Wei²,

et al. 2023

Metrology, Inspection, and Process Control XXXVII

View full text Add to dashboard Cite

Two of most important parameters for the integrated circuit manufacturing are linewidth and overlay. The linewidth uniformity is guaranteed by good exposure tooling, photoresist material, photomasks, Optical Proximity Correction (OPC), optimized patterning process, and good metrology. The linewidth metrology utilized the Scanning Electron Microscope (SEM) directly, which accuracy is entirely determined by the equipment. The overlay metrology quality, however, not only depends on the equipment performance, but can also depend on the substrate quality. There are two types of overlay measurement techniques, i.e., the Image Based Overlay (IBO) and the Diffraction Based Overlay (DBO). In this paper, we will focus our study on a 3 nm Complementary FET (CFET) metal layer overlay. The dimensions of a 3 nm logic design can be as small as 20~24 nm for the Fin Pitch (FP) and 36~48 nm for the Contacted Poly Pitch (CPP) and a On Product Overlay (OPO) of 2.5 nm is required. We will report our study on the DBO for the metal to metal overlay under typical 3 nm logic CFET design rules and a proposed film stack.

show abstract

Section: The Dbo Simulation Results In 3 Nm Cfet Beol Metal Layer Fil...mentioning

confidence: 99%

A study of diffraction-based overlay (DBO) on a 3nm CFET metal layer

Wei²,

et al. 2023

Metrology, Inspection, and Process Control XXXVII

View full text Add to dashboard Cite

show abstract

“…[44] The dual damascene structures with 10.5 nm vias in trenches of the same width were defined using EUV lithography and a self-alignment for the vias in the direction of the etched trenches. [16] The vias were etched in a dielectric stack of dense low-k material SiOCH with k-value of 3.0% and 7% porosity, using 20 nm SiO 2 as dielectric hard mask and 10 nm SiCN as the etch stop layer before opening on Ru serving as the bottom growth surface, as described by Vega Gonzalez et al [16] After the dry etch and post-etch wet clean to remove the TiN metal hard mask, the stack was annealed ex situ before the DMA-TMS treatment for 10 min at 300 °C in a 5% H 2 /N 2 atmosphere to remove any moisture left behind in the low-k surface. Most of the blanket and patterned substrates were treated with DMA-TMS for passivation.…”

Section: Methodsmentioning

confidence: 99%

“…[ 44 ] The dual damascene structures with 10.5 nm vias in trenches of the same width were defined using EUV lithography and a self‐alignment for the vias in the direction of the etched trenches. [ 16 ] The vias were etched in a dielectric stack of dense low‐k material SiOCH with k‐value of 3.0% and 7% porosity, using 20 nm SiO 2 as dielectric hard mask and 10 nm SiCN as the etch stop layer before opening on Ru serving as the bottom growth surface, as described by Vega Gonzalez et al. [ 16 ] After the dry etch and post‐etch wet clean to remove the TiN metal hard mask, the stack was annealed ex situ before the DMA‐TMS treatment for 10 min at 300 °C in a 5% H 2 /N 2 atmosphere to remove any moisture left behind in the low‐k surface.…”

Section: Methodsmentioning

confidence: 99%

“…Barrierless Ru metallization has demonstrated excellent performance and reliability properties. [16][17][18][19] Nanoscale contact holes aligned above a metal surface can be filled with barrierless Ru metal (Figure 1) to create low-resistance Ru-Cu hybrid interconnect structures. [2,3] To achieve this, Ru must selectivity grow on metals like Cu, W, Mo, or Ru, rather than on non-growth surfaces such as SiO 2 and low-k dielectric materials.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Selectivity and Growth Rate Modulations for Ruthenium Area‐selective Deposition by Co‐Reagent and Nanopattern Design

Mandal,

van der Veen,

Rahnemai Haghighi

et al. 2024

Adv Materials Technologies

View full text Add to dashboard Cite

Area‐selective deposition (ASD) is a bottom‐up technique that provides numerous opportunities for nanoelectronic device fabrication. For example, advanced nano‐interconnect structures with barrierless metals like Ru in the contact holes can be created by Ru ASD with the bottom metals as growth surfaces and dielectrics as non‐growth surfaces. This work investigates Ru ASD by chemical vapor deposition (CVD) on industrially relevant substrates and nanopatterns and reveals how selectivity and growth rate are modulated by the CVD conditions and type of nanopattern. For low‐k dielectric/Cu substrate combinations, the selectivity reverses from metal‐on‐metal to metal‐on‐dielectric upon only changing the CVD co‐reagent from H2 to NH3. In contrast, NH3 is the preferred co‐reagent for SiO2‐TiN line patterns with critical dimension (CD) of 40 nm due to the more favorable adsorption and diffusion kinetics that cause growth rate and selectivity enhancement. Consistent with a diffusion‐mediated mechanism, the growth rate enhances even more for Ru CVD on nanoscale contact holes with CD of 10.5 nm, becoming 2.4 times higher as compared to unpatterned substrates. Thus, the ASD process changes drastically when pattern dimensions reach the nanoscale. The reported insights facilitate rational design of metal ASD processes for multiple applications in nanofabrication.

show abstract