Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Mansour, Marwa; Mansour, Islam

doi:10.1002/cta.3363

Cited by 4 publications

(2 citation statements)

References 34 publications

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“…When the channel bandwidth (BW) equals 100MHz, and assume the minimum signal-to-noise ratio (SNR min ) is 16 dB under the QPSK modulation technique and bit error rate (BER) less than 10 − 15 as illustrated in [2]. While the input third-order intercept point (IIP3) is estimated from Eq.…”

Section: A Radio Frequency Receiver Post -Layout Simulation Resultsmentioning

confidence: 99%

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ULP Radio Frequency Receiver for mm-wave Applications using 130 nm CMOS with Harvesting DC Supplies

Mansour

2022

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This paper presents an Ultra-Low-Power (ULP), high integration, and wide bandwidth low-IF radio frequency receiver for millimeter-wave (mm-wave) applications using 130 nm CMOS technology. The proposed radio receiver is composed of a low-noise driver stage implemented using a complementary current reuse common gate with an active shunt feedback configuration, and an in-phase/quadrature of phase (I/Q) demodulator. The driver stage is used to expand the input RF impedance matching with acceptable linearity and gain at an ultra-low DC power dissipation. Moreover, the transformer coupling between the trans-conductance and switching stages is used to separate the DC bias between those two stages, the transformer is a high coupling factor wideband width 5-ports transformer. The DC supplies of the proposed mm-wave radio frequency receiver are implemented using two energy-harvesting voltage doubler designs. The proposed mm-wave radio receiver dissipates 0.475 mW from a 1.1 V DC supply and it has a power conversion gain (CG) of 6.3 dB with 3-dB frequency bandwidth of about 10 GHz (22-32GHz). The two energy-harvesting systems are implemented on the RO4003C substrate material and using the HSMS2852 Schottky diode. The first suggested RF voltage doubler with series resonance feedback and parallel resonance operates at dual frequency bands of 850 and 1400MHz and obtains a peak conversion efficiency of 59%, saturated output DC voltage is 2.5V, and the conversion efficiency is 40% at RF input power of -10dBm. The proposed voltage doubler achieves the required DC supply parameters (1.1V and 450uA) at an RF input power of 0dBm. Otherwise, the second suggested negative voltage rectifier has a maximum simulated conversion efficiency of 65%, saturated negative DC voltage is -3.5V at RF input power of 8 dBm, and the conversion efficiency is 45% at RF input power of -10dBm. The suggested negative voltage rectifier obtains the required DC supply parameters (-0.5V and no current condition) at -10dBm input power.

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Section: A Radio Frequency Receiver Post -Layout Simulation Resultsmentioning

confidence: 99%

“…After that, the baseband signal is ampli ed to the desired level by VGAs. The link budget coe cients calculation is described in [2].…”

Section: Introductionmentioning

confidence: 99%

ULP Radio Frequency Receiver for mm-wave Applications using 130 nm CMOS with Harvesting DC Supplies

Mansour

2022

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Comprehensive study of Class‐‐E/F₂ and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

Mansour,

Mansour

2024

Circuit Theory & Apps

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This paper presents a comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers (PAs) designed for 35–42 GHz millimeter‐wave applications, utilizing a 130 nm CMOS process. The proposed RF PAs are well suited for wide frequency‐band millimeter‐wave and 5G radio transmitters. A comprehensive study of limiting factors in amplifier efficiency is presented in this paper. The study encompasses an analysis of all the factors that restrict the efficiency of the switched power amplifier. The first proposed power amplifier is based on the Class E/F2 architecture, comprising a parallel capacitor, second harmonic resonance circuit, and output matching network. Conversely, the second suggested power amplifier is constructed using the inverse Class‐‐F topology, which includes harmonic termination and matching networks. The harmonic termination circuit incorporates a second harmonic resonance network and utilizes a parasitic capacitor to control the harmonic components. Both the proposed Class E/F2 and inverse Class‐‐F architectures are employed to reshape the drain current and voltage waveforms, aiming to reduce the overlap between them and, consequently, improve efficiency. The suggested power amplifiers comprise a driver Class‐‐AB stage and a power stage constructed based on either the Class E/F2 architecture or inverse Class‐‐F topology, utilizing harmonic termination networks at the output load. Two new designs of high‐Q factor on‐chip finger capacitors have been implemented to improve efficiency and radio frequency performance. Achieving input matching and inter‐stage matching is facilitated by employing two novel on‐chip transformers designed for maximum power transfer. Additionally, an inter‐stage matching inductor is utilized in a cascode configuration to enhance the overall RF performance. The on‐chip transformers, inductors, and finger capacitors are designed using the HFSS software program. S‐parameter files (SNP files) of the designed on‐chip components are extracted and inserted into the simulation tool to ensure accurate results. The proposed Class E/F2 power amplifier achieves a constant power of 14.9 dBm, an extreme power added efficiency (PAE) of 11.7%, and a maximum gain of 13.74 dB. In contrast, the suggested inverse Class‐‐F power amplifier attains a constant power of 15.4 dBm, a peak PAE of 12.6%, and a maximum gain of 14.8 dB. The DC power consumption is 73 and 66 mW for the proposed Class E/F2 and inverse Class‐‐F PAs, respectively, while their active sizes are 0.14 and 0.2 mm2.

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Battery‐free ultra‐low‐power radio‐frequency receiver for mm‐wave applications using 130‐nm CMOS technology with harvested DC supplies

Mansour,

Mansour

2024

Circuit Theory & Apps

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SummaryThis paper presents a battery‐free ultra‐low‐power (ULP), highly integrated, and wide‐bandwidth low‐IF radio‐frequency (RF) receiver designed for millimeter‐wave (mm‐Wave) applications, utilizing 130‐nm CMOS technology. The suggested RF receiver is suitable for K‐band (n258) at 26 GHz, Ka‐band (n261 and n257) at 28 GHz, and the LMDS band at 28 GHz in fifth‐generation applications. The proposed radio receiver consists of a low‐noise driver stage implemented using a complementary current‐reuse common gate with an active shunt feedback configuration and an in‐phase/quadrature‐phase (I/Q) demodulator. The proposed RF receiver employs transformer coupling to isolate the DC path between the transconductance stage (RF stage) and the switching stage (IF stage). The driver stage expands the RF input impedance while maintaining acceptable linearity and gain with ultra‐low DC power dissipation. The DC supplies for the proposed mm‐Wave RF receiver are generated using two novel energy‐harvesting voltage doubler circuits to provide positive and negative voltages. The proposed mm‐Wave radio receiver consumes 0.475 mW from a 1.1 V DC supply and exhibits a power conversion gain (CG) of 6.3 dB, with a 3 dB frequency bandwidth extending from 22 to 32 GHz. The input 1‐dB compression point (P1dB) of the RF receiver is −2.65 dBm, and the input third‐order intercept point (IIP3) is 7.35 dBm. With a sensitivity of −66.5 dBm at a 100 MHz channel bandwidth and a dynamic range of 63.85 dB, the suggested receiver demonstrates notable performance characteristics. The proposed radio receiver boasts an excellent figure of merit (FoM) at 215 dB, surpassing published works by a margin of 8–31 dB. The primary positive supply voltage is derived from a double‐band positive voltage doubler with series resonance feedback and parallel resonance networks, efficiently achieving the desired DC voltage and output current (1.1 V and 450 μA). Meanwhile, the negative gate bias is provided by a negative voltage doubler, ensuring the necessary negative voltage (−0.5 V) without any current conditions.

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Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Cited by 4 publications

References 34 publications

ULP Radio Frequency Receiver for mm-wave Applications using 130 nm CMOS with Harvesting DC Supplies

ULP Radio Frequency Receiver for mm-wave Applications using 130 nm CMOS with Harvesting DC Supplies

Comprehensive study of Class‐‐E/F₂ and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

Battery‐free ultra‐low‐power radio‐frequency receiver for mm‐wave applications using 130‐nm CMOS technology with harvested DC supplies

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Three‐stage transformer‐coupled CMOS power amplifier for millimeter‐wave applications using 130 nm CMOS technology

Cited by 4 publications

References 34 publications

ULP Radio Frequency Receiver for mm-wave Applications using 130 nm CMOS with Harvesting DC Supplies

ULP Radio Frequency Receiver for mm-wave Applications using 130 nm CMOS with Harvesting DC Supplies

Comprehensive study of Class‐‐E/F2 and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process

Battery‐free ultra‐low‐power radio‐frequency receiver for mm‐wave applications using 130‐nm CMOS technology with harvested DC supplies

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Comprehensive study of Class‐‐E/F₂ and inverse Class‐‐F power amplifiers for mm‐Wave systems utilizing 130 nm CMOS process