ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)
DOI: 10.1109/icecs.2001.957620
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Threshold-gates in arithmetic circuits

Abstract: In this paper the design of digital CMOS threshold logic circuits for low power applications is investigated. Two different basic elements for threshold circuits are presented. These circuits are characterized with regard to power and speed. More complex functions, i.e. a 1-bit full adder and an 8-bit carry-lookahead adder are given. Moreover an approach for the determination of the WIL-ratios for the transistors with an evolutionary algorithm is discussed.

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“…Output wired inverters discovered by Lerch [98]. [93]. Still, these TLGs are extremely fast, while exhibiting high power consumption (assumable when traded-off for speed), as well as narrow noise margins.…”
Section: A Early Conductance/current Solutionsmentioning
confidence: 99%
“…Output wired inverters discovered by Lerch [98]. [93]. Still, these TLGs are extremely fast, while exhibiting high power consumption (assumable when traded-off for speed), as well as narrow noise margins.…”
Section: A Early Conductance/current Solutionsmentioning
confidence: 99%