Threshold Voltage Modeling of Fully Depleted Nanoscale Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel by Considering Drain Bias

Abstract

The threshold voltage (V th ) was modeled in a simple closed form by considering drain bias (V DS ) for fully depleted (FD) symmetric doublegate (DG) n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with doped short channels. The V th model using only two parameters (D G and D D ) is based on V th0 (V th at low V DS ), and derived from the diffusion current of doped DG MOSFETs that was modeled using surface potential (È s ). D G and D D are parameters for considering the gate bias (V GS ) dependence and V DS dependence, respectively, in the diffusion current model. Our compact V th model predicted the threshold voltage behavior by considering V DS more accurately than the constant current (CC) method down to a channel length (L) of 30 nm.

Current–Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

“…for DG MOSFETs in saturation region; ð6Þ where C 0 ox is the effective oxide capacitance, 24) V th (¼ V th0 À D D Á V DS =D G ) is the threshold voltage at a high V DS , 25) and L D2 is the channel-modulated length. If we change W in Eqs.…”

Subthreshold behavior models for nanoscale junctionless double-gate MOSFETs with dual-material gate stack

“…[1][2][3][4] A symmetric structure and simple fabrication process make the DG structure stand out among these new structures and they have become a hot research topic. [5][6][7] However, the fabrication of multi-gate MOSFETs at the nanoscale is still another problem. The formation of ultrasharp source and drain junctions imposes drastic conditions on the doping technique and thermal budget.…”