Threshold voltage shift instability induced by plasma charging damage in MOSFETs with high-k dielectric

et al. 2011

Plasma-induced charging damage (PCD) to a metal–oxide–semiconductor field-effect transistor (MOSFET) with a high-k dielectric was studied in detail using a capacitively coupled plasma reactor for various exposure times. From the drain current versus gate voltage characteristics, we observed the threshold voltage shift (ΔV th) and the increase in reverse-leakage current (I j) at the n+/p junction in plasma-exposed n-channel MOSFETs. The observed ΔV th in the negative direction was due to positive trap-site creation in the high-k dielectric. The combined effect by PCD increased off-state leakage current (I off) in n-channel MOSFETs, however, the I j increase was found to be dominant in the I off increase. By employing a capacitance-measurement technique, we clarified that the I j considerably was increased at the junction by PCD, whereas the maximum capacitance at the junction in accumulation decreased. We also identified that the generated defect site density (n d) at the junction induces the observed I j increase as a trap-assist tunneling site.

Section: Resultsmentioning

confidence: 88%

“…One can clearly see the increase in off-state leakage current at V g ¼ 0 V (I off ) as well as the threshold voltage shift ÁV th owing to PCD. The observed ÁV th is considered to be caused by the trap site created in the high-k gate dielectric 11,16). I off and ÁV th increase with an increase in plasma-exposure time.…”

mentioning

confidence: 99%

Comparative Study of Plasma-Charging Damage in High-k Dielectric and p–n Junction and Their Effects on Off-State Leakage Current of Metal–Oxide–Semiconductor Field-Effect Transistors

Kamei

Takao

et al. 2011

“…The electrical thicknesses determined by capacitance-voltage (C-V) measurements were $2:7 and $7:4 nm for the high-k gate stack and SiO 2 , respectively. Note that since a high-k gate stack exhibits a unique and unstable V th shift caused by charging damage, 49,51) we primarily focus on the V th shift of n-and p-channel MOSFETs with SiO 2 . The gate width (W) and length (L) of MOSFETs were W=L ¼ 10=10, 30/30, and 100/100 mm, giving gate areas of 100, 900, and 10000 mm 2 , respectively.…”

Section: Methodsmentioning

confidence: 99%

Comprehensive Modeling of Threshold Voltage Variability Induced by Plasma Damage in Advanced Metal–Oxide–Semiconductor Field-Effect Transistors

Nakakubo

Matsuda

et al. 2010

Threshold voltage shift (ΔV th) and its variation induced by plasma processing were investigated in detail. Two damage mechanisms occurring in an inductively coupled plasma reactor were focused on in this study; the charging damage induced by the conduction current from plasma and the physical damage attributed to the bombardment of high-energy ions. Regarding the charging damage, ΔV th was found to show a power-law dependence on antenna ratio for both SiO2 and high-k gate dielectrics in metal–oxide–semiconductor field-effect transistors (MOSFETs). The observed dependence was also confirmed from the results of a constant-current stress test, indicating that the plasma plays the role of the current source in terms of the charging damage. As for the physical damage, the recess structure in source/drain extension regions was focused on as a possible cause of ΔV th. The depth of the recess (d R) formed by the physical damage was studied using Si wafers exposed to various plasma conditions and subsequently analyzed for surface damage. The recess depth determined from the experiments and classical molecular dynamics simulations exhibits a power-law dependence on potential drop across the sheath between the plasma and the device surface (V p-V dc), which is used as a practical measure of the damage. On the basis of the above results, ΔV th due to the physical damage was calculated by technology computer-aided design (TCAD) device simulation for n- and p-channel MOSFETs with the recess structure. ΔV th shows a linear dependence on recess depth for both n- and p-channel MOSFETs, resulting in the power-law dependence on (V p-V dc) via d R. These findings provide a simple relationship among the variations of ΔV th, antenna ratio, and plasma parameters. By taking into account the findings that the MOSFET with high-k dielectrics shows a larger ΔV th due to the charging than that with SiO2, and that the MOSFETs with a smaller gate length indicate a larger ΔV th due to the Si recess structure, we can conclude that larger amount of plasma damage induces the larger ΔV th variations, i.e., the V th variability induced by the plasma damage is difficult to suppress and will become crucial to the fabrication of future advanced devices. The proposed relationship is useful as a guideline to suppress the ΔV th variations caused by plasma damage.

“…Nishida et al experimentally revealed the presence of carrier capturing sites in SiOC films after plasma exposure using an on-the-fly C-V technique. 68) With respect to the influence of PPD on ULSI circuit designs, it is predicted that PPD (the same as PCD) induces the parameter variability of MOSFETs in ULSI circuits, 42,133,134) in addition to L g variation 135,136) or impurity fluctuation. 137,138) For detail, see the literatures.…”

Section: Ppd Range Theory and Device Performance Degradationmentioning

confidence: 99%

Characterization techniques of ion bombardment damage on electronic devices during plasma processing—plasma process-induced damage

2021

Plasma processing plays an important role in manufacturing leading-edge electronic devices such as ULSI circuits. Reactive ion etching achieves fine patterns with anisotropic features in metal-oxide-semiconductor field-effect transistors (MOSFETs). In contrast, it has been pointed out over the last four decades that plasma processes not only modify the surface morphology of materials but also degrade the performance and reliability of MOSFETs as a result of defect generation in materials such as crystalline Si substrate and dielectric films. This negative aspect of plasma processing is defined as plasma (process)-induced damage (PID) which is categorized mainly into three mechanisms, i.e. physical, electrical, and photon-irradiation interactions. This article briefly discusses the modeling of PID and provides historical overviews of the characterization techniques of PID, in particular, by the physical interactions, i.e. ion bombardment damage.