Threshold-voltage shift model based on electron tunneling under positive gate bias stress for amorphous InGaZnO thin-film transistors

Quantitative Analysis of Positive-Bias-Stress-Induced Electron Trapping in the Gate Insulator in the Self-Aligned Top Gate Coplanar Indium–Gallium–Zinc Oxide Thin-Film Transistors

“…Figures 3a and 3b demonstrate the energy distribution of the subgap DOS extracted using the MPCV technique before and after the application of the PBTS (VGS = 40 V, VDS = 0 V, 80 °C) for a stress time (tst) of 5000 s. The results presented in Figure 3 show that the difference between the energy distribution of the subgap DOS extracted from the TFT before and after PBTS was minimal, indicating that the electron injection from the channel (IGZO) to the gate dielectric (SiO2) in the fabricated SA-TG IGZO TFTs caused the PBTS-induced transfer curve shift observed in Figure 2. Subsequently, we validated the assumption made in previous reports that electrons are trapped in the dielectric trap states only at a single energy level during PBTS in IGZO TFTs [10]. Figure 4 illustrates the time evolution of the threshold voltage shift (ΔVTH) during the stress (VGS = 40 V, VDS = 0 V, 80 °C, tst = 5000 s) and subsequent recovery (VGS = 0 V, VDS = 0 V, 80 °C, tst = 10,000 s) phases.…”

“…There were three different cases of trapped electrons in gate dielectrics under PBTS in IGZO TFTs. As depicted in Figure 7a, under a small VGS for a short tst, the electrons could not transfer to the position x0 and tunnel back easily to IGZO; as VGS and tst increased, the electrons tunneled deeper into the gate dielectric, and could not tunnel back easily to IGZO until they were trapped in ET below EF [10]. Further, as VGS and tst continued to increase, the trap states located near x0 were filled with electrons and thus could no longer capture them.…”

“…To date, only a few studies have quantitatively analyzed PBTS-induced electron trapping in the gate dielectric in IGZO TFTs. Some previous studies have successfully established analytical models for the extraction of a detailed trapped electron distribution within the gate dielectric after PBTS [9,10]. However, the assumptions made in these studies are somewhat problematic.…”

The influence of ZnO layer thickness on the performance and electrical bias stress instability in ZnO thin film transistors

“…where σ is the electrical conductivity of the film, V ds is the source to drain voltage, W is the active channel width and L is the channel length. Despite the advantages offered by ZnO TFTs, threshold voltage (V T ) instability resulting from prolonged application of gate bias is one of the major challenges hindering its eventual integration into large area electronic technology [10,14,15]. The purpose of this work is to demonstrate that both performance and gate bias stress related electrical instability in ZnO TFTs can be modulated via thickness optimisation of the ZnO active layer.…”

Geometrically designed amorphous oxide semiconductor heterojunction thin-film transistors for enhanced electrical performance and stability

“…3(d). In the case of single-layer IZTO TFTs, ΔV th was +11.3 V. Also, the ZTO TFTs without the IZTO FCL exhibited ΔV th of +5.81 V. Notably, a substantial decrease of ΔV th was observed in the IZTO/ZTO TFTs with L FCL of 45 μm, showing ΔV th of +2.46 V. Under PBS conditions, electrons in the channel can be trapped at the gate dielectric/channel interface 31) or tunnel into the gate dielectric layer, 32) resulting in a positive parallel shift of the transfer curve. Moreover, ionized oxygen vacancies in the bulk oxide semiconductor can capture electrons, causing a similar positive V th shift.…”