Threshold Voltage Variability in Nanosheet GAA Transistors

Vardhan, P. Harsha; Amita,; Ganguly, Swaroop; Ganguly, Udayan

doi:10.1109/ted.2019.2933061

Cited by 41 publications

(12 citation statements)

References 8 publications

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“…Three-dimensional simulations of NS-TFET are done using COGENDA-TCAD software [24]. The physical models such as the DD model, Lombardi mobility model, Kane's BTBT model, and SRH model are evaluated at each mesh node using TCAD software.…”

Section: Resultsmentioning

confidence: 99%

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Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Jain

Sawhney

Kumar

et al. 2021

Silicon

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In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10 -16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 10 11 has been achieved. The device exhibits a high transconductance of 3.022x10 -5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

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Section: Resultsmentioning

confidence: 99%

“…The Lombardi model is invoked for carrier mobility in the inversion layer of the NS-TFET device. This mobility model incorporates bulk mobility, mobility due to surface charge, and scattering [24]. Gate tunneling plays a pertinent role in NS-TFET devices.…”

Section: Device Structurementioning

confidence: 99%

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Jain

Sawhney

Kumar

et al. 2021

Silicon

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“…The GAA architecture promises numerous advantages over FinFET such as better electrostatic control, higher drive current, improved power, and performance trade-off through higher design flexibilities. While the GAA's superior performance over the FinFET has been demonstrated [1][2], it remains conditional: sub-nanometer device dimension control becomes more problematic as the device performance is highly sensitive to small variations [3]. The complex process leads to various new challenges.…”

Section: Introductionmentioning

confidence: 99%

“…GAA devices face regular and common process variations, such as line edge and surface roughness, gate-edge roughness [4], non-vertical sidewall angles, non-uniform work function due to metal gate granularity [5][6], random dopant fluctuations, etc. In addition, GAA are prone to new types of process variability challenges and within transistor sheet-to-sheet variation since the GAA have several nanosheets in parallel [3]. These new challenges include 1) the non-uniform thicknesses in the initial alternating Si-SiGe superlattice stacks, 2) random local Ge composition fluctuation, 3) germanium thermal diffusion inducing intermixing Si-SiGe, which can lead to aggravated sheet thickness and inner-sheet spacing variations, 4) the cavity etches of each of the sacrificial SiGe nanosheets, 5) the inner spacers' thickness filling the previously formed cavities [7], 6) the post-channel release widths, thicknesses, extensions, and inner spacers, and 7) the high-k and metal gate (TiN, TaN) depositions around each of the nanosheets, which are meant to be grown equally thick and conformal.…”

Section: Introductionmentioning

confidence: 99%

Mueller matrix spectroscopy and physics-based machine learning for gate-all-around sheet-specific metrology

Chouaib¹,

Chou²,

Dimastrodonato³

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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The complex vertically stacked gate-all-around (GAA) manufacturing process drives the demand for more challenging inline metrology requirements. GAA technology with specific technical requirements starts from the first process step, 1) the superlattice, where the multi-stack Si/SiGe pairs must be grown defect-free with matched Si nanosheet thicknesses, and %Ge per layer, sharp interfaces, and a minimized subsequent thermal Ge diffusion across the stacks. More critical steps, among others, are the 2) partial recess of the sacrificial SiGe layers that precede 3) the inner spacers which prevent a channel to source/drain short circuit and reduce the parasitic capacitance, and 4) the channel release process at the “remove poly gate” module, where the SiGe is selectively removed before the high-k metal gate. Driven by tight performance control, a sheet-specific metrology solution is highly desired at each of the above four critical steps. The ideal solution for such an application is non-destructive, precise, accurate, and highly productive. In this paper, a scatterometry critical dimension (SCD) solution for the GAA sheet-specific measurement from various GAA structures is presented. The SCD solution includes an advanced and optimized full Mueller Matrix spectroscopic ellipsometry in conjunction with a physics-assisted machine learning (ML) algorithm. Additionally, the best methodology to address the solution's robustness to process variation is described and presented. It will be shown that an optimized signal-to-noise ratio combined with ML can provide a superior optical metrology solution to the growing challenge in GAA applications.

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“…The work function of TiN depends on the ratio of Ti to N and metal thickness [7][8][9]16]. An increase in TiN thickness changes WFM and V t [11,17]. In addition to metal thickness, metal gate granularity is another determinant that varies V t [18,19].…”

Section: Introductionmentioning

confidence: 99%

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

Chang¹,

Li²,

Hsu³

et al. 2021

IEEE Open J. Nanotechnol.

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High-k metal gate technology improves the performance and reduces the gate leakage current of metal-oxide-semiconductor field-effect transistors (MOSFETs). This study investigated four different work function metal (WFM) stacks in the gate of fin field-effect transistors (FinFETs) on the same substrate. These devices not only successfully produced distinct levels of threshold voltages (|V t |) but also converted n-to p-type features merely by adding p-type WFM in the gate of the MOSFETs. All of the devices satisfied short-channel effects with shrinking channel length. The gate-to-body electric field induced drain leakage due to the nature of bulk FinFETs. However, the n-and p-type gate stacks presented different gate current leakage. For reliability, hot carrier injection (HCI) could have a higher reliability impact than the negative-bias temperature instability (NBTI) for p-MOSFET, although the stress voltage of HCI was roughly half that of the NBTI test. This multi-threshold voltage tuning allows designers to design CMOS and choose the trade-off between low power consumption and high performance on the same platform.

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Threshold Voltage Variability in Nanosheet GAA Transistors

Cited by 41 publications

References 8 publications

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Mueller matrix spectroscopy and physics-based machine learning for gate-all-around sheet-specific metrology

Modifying Threshold Voltages to n- and p- Type FinFETs by Work Function Metal Stacks

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