Through-Silicon Vias Using Bosch DRIE Process Technology

Laermer, Franz; Urban, Andrea

doi:10.1007/978-1-4419-7276-7_9

Cited by 6 publications

(7 citation statements)

References 13 publications

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“…A closer view on the sidewalls (see the magnified view of the top of the trench in Figure 4 a), reveals that scalloping has been greatly reduced to a residual roughness. Consequently, and as expected, the cycle time is a relevant knob to minimize the sidewall defects in the STiGer, similarly to what is reported for the Bosch process [ 9 ].…”

Section: Resultssupporting

confidence: 76%

“…As pointed out in the previous parts, minimizing the sidewall roughness, in particular the standard scalloping, is relevant for several applications, like TSV filling. This is directly possible by reducing the cycle time thanks to the progress in the hardware of etching tools (“ultrafast gas-switching”) [ 9 ].…”

Section: Resultsmentioning

confidence: 99%

“…In most cases, the etch step is isotropic and achieved with an SF 6 plasma. In the passivation step, all the etched surface is coated with a fluoropolymer layer deposited by a C 4 F 8 plasma (note that other fluorocarbon chemistries are also possible [ 2 , 7 , 8 , 9 ]). In each subsequent cycle, ions break though the passivation layer at the etch front and, from one cycle to the other, an isotropic cavity is etched underneath the previous one.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Comparison between Bosch and STiGer Processes for Deep Silicon Etching

et al. 2021

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The cryogenic process is well known to etch high aspect ratio features in silicon with smooth sidewalls. A time-multiplexed cryogenic process, called STiGer, was developed in 2006 and patented. Like the Bosch process, it consists in repeating cycles composed of an isotropic etching step followed by a passivation step. If the etching step is similar for both processes, the passivation step is a SiF4/O2 plasma that efficiently deposits a SiOxFy layer on the sidewalls only if the substrate is cooled at cryogenic temperature. In this paper, it is shown that the STiGer process can achieve profiles and performances equivalent to the Bosch process. However, since sidewall passivation is achieved with polymer free plasma chemistry, less frequent chamber cleaning is necessary, which contributes to increase the throughput.

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Section: Resultssupporting

confidence: 76%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Comparison between Bosch and STiGer Processes for Deep Silicon Etching

et al. 2021

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“…The formation of wall roughness in the Bosch process, called scallops [13], is well known to occur due to alternating passivation followed by an isotropic etching process, whose size depends on the length of one cycle of silicon deep etching. For our process the typical size of scallops is 300-500 nm.…”

Section: Fabrication Technologymentioning

confidence: 99%

Superconducting TSV contact for cryoelectronic devices

Filippov,

Anikanov,

Rykov

et al. 2023

Supercond. Sci. Technol.

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This work focuses on the fabrication of niobium through silicon vias (TSV) superconductors interconnects. The effect of supercycle of sequential oxidation and chemical etching process on the through-etch wall quality was investigated. It was experimentally shown that the use of supercycle in the fabrication process leads to significant improvement of the TSV wall quality and removal of the defect type—scallops. After 12 times repetitions of supercycles a dissipative bonding of superconducting strips on the front and back side of the sample is observed. The critical current density of such coupling is 5 × 104 A cm−2. The critical ratio of substrate thickness to hole diameter at which electrical coupling is formed is 3:1.

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“…5(a). After the DRIE Bosch process [31], the sidewall maximum peak-tovalley roughness measured by atomic force microscopy (AFM) was ∼977 nm with a root mean squared (RMS) value of ∼173 nm. The smoothing process tremendously improved the surface roughness of etched sidewalls resulting in a maximum peak-to-valley roughness and an RMS roughness of ∼768 nm and ∼106 nm, respectively.…”

Section: A Gold Sputteringmentioning

confidence: 99%

Pushing the Limits of Bonded Multi-Wafer Stack Heights While Maintaining High Precision Alignment

Narimannezhad

Jennings

Weber

et al. 2016

J. Microelectromech. Syst.

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The last decade in advanced microelectronics has shown great interest in 3-D architectures, which was paved by multi-wafer alignment technologies. However, many limitations remain in the fabrication of ultratall stacks as the alignment becomes more challenging and very costly. In this paper, a new cost-effective alignment technique was employed using a set of sapphire rods in through-wafer holes. Cross-sectional analysis, edge profilometry, and electron transmission tests showed ∼2 µm alignment tolerances over 1 cm and ∼4 µm over 10-cm tall stacks. An off-angle gold sputtering method was developed to fully coat vias of 5:1 aspect ratio before bonding. Also, a new "Stamping" technique is introduced to coat the vias to a desired height where necessary. In this paper, parallel microtubes with the aspect ratios of 1000:1 were formed by aligning ∼200 wafers, each including 20 000 gold-coated vias for storing charged particles.[2016-0049]

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Through-Silicon Vias Using Bosch DRIE Process Technology

Cited by 6 publications

References 13 publications

Comparison between Bosch and STiGer Processes for Deep Silicon Etching

Comparison between Bosch and STiGer Processes for Deep Silicon Etching

Superconducting TSV contact for cryoelectronic devices

Pushing the Limits of Bonded Multi-Wafer Stack Heights While Maintaining High Precision Alignment

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