2020
DOI: 10.1109/jssc.2020.2970709
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Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation

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Cited by 125 publications
(69 citation statements)
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“…Third, for large-scale networks, we adopted some optimization mechanisms to ensure that multiple networks could run efficiently on the chip. These mechanisms included a point-to-point routing scheme and an adjacent multicast routing strategy 17 . The cores communicated with each other via a 2D-mesh method.…”
Section: Flexible Module Cooperationmentioning
confidence: 99%
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“…Third, for large-scale networks, we adopted some optimization mechanisms to ensure that multiple networks could run efficiently on the chip. These mechanisms included a point-to-point routing scheme and an adjacent multicast routing strategy 17 . The cores communicated with each other via a 2D-mesh method.…”
Section: Flexible Module Cooperationmentioning
confidence: 99%
“…Second, to adapt to dynamic environments, we developed a high-level decision-making module based on a hybrid neural state machine (HNSM) to integrate different modules flexibly, providing the capability to oversee and schedule different information flows, as well the capacity to be extended for dealing with increasing tasks during the implementation process. Third, inspired by neocortical regions organized with cortical columns 29 , we developed a scalable computing system based on our cross-paradigm neuromorphic chip, Tianjic, and a customized tool chain for hardware and software co-design 16,17 . The system has the potential to underpin brain-inspired system evolution and growth, similar to that exhibited in the human brain 30 .…”
mentioning
confidence: 99%
“…In terms of the integration of both neuromorphic primitives (e.g., spiking neural networks) and DNNs, there is the Tianjic chip [17,62], a multi-chip many-core architecture providing a hybrid platform toward artificial general intelligence. The Tianjic chip, consisting of 156 functional cores, shows significant improvement in both throughput (1.6× to 10 2 ×) and power efficiency (12× to 10 4 ×) compared with the GPU.…”
Section: Multi-chip Many-core Architecturesmentioning
confidence: 99%
“…Although all chips are functional in the multi-chip many-core system, different workloads may occupy different number of chips/cores, since in these spatially weight-stationary mappings, the number of cores consumed is kind of proportional to the model size. Configuration parameters are summarized in Table 1, which are collected from existing multi-chip many-core architectures [17,62,67,89,96]. As for hyperparameters in our RL-based approach, the learning rates of the actor and the critic are set as α θ = 0.0002 and α w = 0.001, with the discount factor γ = 0.98.…”
Section: Experiments Setupmentioning
confidence: 99%
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