Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications

Abstract

Power delivery to the tier farthest away from the package in 3D VLSI is challenging. This is because the current provided by the package on the bottom is (1) first used by other tiers before it reaches the top, and (2) delivered using extremely small-size intra and inter-tier vias. Our solution is a tier partitioning method that assigns power hungry cells to the tier closer to the package, which is farther away from the heat spreader. Our study shows that this approach alleviates the IR-drop, power delivery network (PDN) resource usage, and power consumption in the top tier. Moreover, moving the cells to the bottom tier, unlike popular belief, does not cause any serious thermal issues. This is especially true in mobile applications, where heat is dissipated by both the heat spreader and printed circuit board. In summary, our tier-partitioning leads to 24.66% IR-drop reduction, 28.57% PDN resource reduction, and 4% wirelength reduction, with < 1 • C increase in temperature.

Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs

“…An M3D IC can be partitioned at the core-level, block-level, gate-level, and transistor-level. Significant research efforts are being directed towards gate-level design partitioning since transistor-level design partitioning requires extensive redesign of standard cells [6,10] and block-level design partitioning does not fully exploit the benefits of M3D. In [11], a complete RTL-to-GDSII flow for gate-level M3D was proposed and the reduction in power compared to 2D designs was shown.…”

“…We also restrict the total routing resources allocated for power delivery in the top and bottom tier to be between 5% and 25% of the total routing resources. We have chosen these ranges based on the values reported for these parameters in prior work [4][5][6].…”

“…In [5], the impact of PDN on full-chip wire length, routability, power, and thermal effects in M3D ICs was studied. In order to minimize voltage droop in tiers farther away from the I/O pins, a partitioning method that assigns power-hungry blocks to the tier closest to the I/O pins was proposed in [6]. However, there is no previous work that optimizes the PDN to address reliability challenges.…”