Time and energy efficient mapping of embedded applications onto NoCs

Abstract-Systems on Chip (SoCs) congregate multiple modules and advanced interconnection schemes, such as networks on chip (NoCs). One relevant problem in SoC design is module mapping onto a NoC targeting low energy. To date, few works are available on design and evaluation of mapping algorithms. The main goal of this work is to propose some algorithms and evaluate its results and performance with regard to low energy NoC mappings. These include exhaustive and stochastic search methods and heuristic approaches, and some combinations. The use of combined approaches compared to pure stochastic algorithms provides average reductions above 98% in execution time, while keeping energy saving within at most 5% of the best results. In addition, one heuristic provided average reductions in execution time above 90% when compared to pure stochastic algorithms, and obtained better energy saving than combined approaches.

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“…Applications were described with communication quantity, using a communication weight model (CWM) [3].…”

Section: Related Workmentioning

confidence: 99%

“…execution time and energy saving. For each mapping, the energy consumed in the NoC is estimated by applying a method defined in [3]. To compare the quality of mappings, random methods were employed.…”

Section: Experimentationmentioning

confidence: 99%

Evaluation of Algorithms for Low Energy Mapping onto NoCs

Marcon

Moreno

Calazans

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Work in which communication is assumed to be most costly, treats the mapping of tasks to tiles as a cost factor in routing algorithms [4,16,24]. On the other hand, work that stresses computational costs, mostly does not discuss or even consider communication resource management [18].…”

Section: Contribution and Related Workmentioning

confidence: 99%

Run-time Spatial Mapping of Streaming Applications to Heterogeneous Multi-Processor Systems

Hölzenspies

Braak

Kuper

et al. 2009

Int J Parallel Prog

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In this paper, we define the problem of spatial mapping. We present reasons why performing spatial mappings at run-time is both necessary and desirable. We propose what is-to our knowledge-the first attempt at a formal description of spatial mappings for the embedded real-time streaming application domain. Thereby, we introduce criteria for a qualitative comparison of these spatial mappings. As an illustration of how our formalization relates to practice, we relate our own spatial mapping algorithm to the formal model.

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“…A polynomial time heuristic technique called mesh based on-chip interconnection architectures (MOCA) has been presented in [28] for automated design of low energy mesh based NoC architectures. To capture both timing of application communication and communication volume, communication dependence and computation model (CDCM) have been proposed in [29,30]. It maps applications on regular NoC under bandwidth constraint and minimizes average communication delay.…”

mentioning

confidence: 99%