Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

Abstract

An all-digital first-order single-bit ΔΣ time-to-digital converter (TDC) with a pre-skewed bi-directional gated delay line (PS-BDGDL) time integrator with built-in self-quantisation is presented in this study. Pre-skewing is utilised to lower the perstage delay of the BDGDL and minimise the skew errors of BDGDLs. The impact of the strength and timing of pre-skewed is analysed. The reduction of skew errors obtained from pre-skewing is also analysed. A design methodology combating the impact of process uncertainty on the TDC is developed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the impact of process spread on the performance of the TDC can be minimised by adjusting the delay of the key delay blocks and the perstage delay of the gated delay stages. The figure-of-merit of the TDC outperforms reported TDCs alike.

An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation

“…v o 2 ; on the other hand, will drop only after the arrival of v 2 . It was shown in [20] that pre‐skewing will be more effective when the number of pre‐skewed inverters is small and its effectiveness will fade away once the number of pre‐skewed inverters becomes large. Also, the speed gain from pre‐skewing is at the cost of more power consumption and silicon area.…”

Sensitive, Linear, Robust Current-To-Time Converter Circuit for Vehicle Automation Application

“…Several types of voltage-to-time (VTC) and current-to-time (CTC) converters have been proposed for high-speed applications. However, they have very low conversion gains and consume more area and power [15,16]. All of the VTC and CTC designs that have been proposed in recent studies are based on the principle of using the input current or voltage to amplify the output delay.…”

“…However, this method has a very low initial delay and a poor conversion gain. A pre-skewed bi-directional gated delay line has been also proposed in [16] to design a sigma delta-based time-to-digital converter.…”