Time-dependent dielectric breakdown (TDDB) distribution in n-MOSFET with HfSiON gate dielectrics under DC and AC stressing

Izumi, H.; Nakasaki, Yasushi; Fukatsu, Shigeto; Goto, Masakazu; Nagatomo, K.; Inumiya, Seiji; Sekine, Katsuyuki; Mitani, Yuichiro; Yamabe, Kikuo

doi:10.1016/j.microrel.2013.05.010

Cited by 11 publications

(3 citation statements)

References 25 publications

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“…Amongst these features, collector voltage serves as the primary feature for failure analysis. In addition, since the collector voltage is affected by power and temperature fluctuations, so V ce , P and T c are selected [7], [20], [21].…”

Section: Introductionmentioning

confidence: 99%

Online Degradation State Assessment Methodology for Multi-Mode Failures of Insulated Gate Bipolar Transistor

et al. 2020

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Insulated-gate bipolar transistors (IGBTs) are one of the most vulnerable components that account for a significant fraction of inverter and converter failures. This paper conducts a degradation analysis of IGBTs using run-to-failure measurements. Online assessment of the degradation state of IGBTs can prolong normal operation and enable proactive maintenance of the system. The research idea is to find a reliable and robust mechanism for IGBT degradation assessment. This paper developed a prediction interval-based degradation assessment methodology that accurately classifies different health states or degradation levels of IGBTs by adding prediction bounds and using them as a critical value for serious damage. It first computes the prediction interval and then uses the Mahalanobis distance to classify the state into degradation level 1 and degradation level 2, instead of just applying the base algorithm. The developed method outperforms distance-based classification schemes and self-organizing maps for online assessment of degradation levels. It only requires training of 1000 initial points which are assumed to be healthy. Furthermore, the generalizability of the method has been shown by validating the effectiveness of the proposed method on three other modules.

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Section: Introductionmentioning

confidence: 99%

Online Degradation State Assessment Methodology for Multi-Mode Failures of Insulated Gate Bipolar Transistor

et al. 2020

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“…It is then imperative to characterize and understand TDDB under high frequency switching conditions. In fact, studies in Si MOS systems show improvements in time to breakdown under AC stress conditions [7], [8], [9], suggesting the intriguing possibility of similar enhanced reliability for GaN devices. Furthermore, as trapping is very prominent in GaN, understanding the impact of switching on TDDB is particularly important.…”

Section: Introductionmentioning

confidence: 99%

Time-Dependent Dielectric Breakdown Under AC Stress in GaN MIS-HEMTs

Lee

Hurtado

Joh

et al. 2019

2019 IEEE International Reliability Physics Symposium (IRPS)

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“…[4,5] However, there has not been enough systematic analysis about the influence of the MDMA on the TDDB characteristics, especially for the gate-last process. Moreover, TDDB, as one of the most important reliability issues, [6] is widely concerned and will be more important for the beyond 22-nm node. [7] In this paper, we study the electrical and TDDB characteristics of HKMG gate-last PMOS with different MDMA techniques, including the number of deposition/annealing (D&A) cycles and the D&A time.…”

Section: Introductionmentioning

confidence: 99%

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high- k /metal gate last process

Wang¹,

Yang²,

Xu³

et al. 2015

Chinese Phys. B

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A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device's performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms.

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Time-dependent dielectric breakdown (TDDB) distribution in n-MOSFET with HfSiON gate dielectrics under DC and AC stressing

Cited by 11 publications

References 25 publications

Online Degradation State Assessment Methodology for Multi-Mode Failures of Insulated Gate Bipolar Transistor

Online Degradation State Assessment Methodology for Multi-Mode Failures of Insulated Gate Bipolar Transistor

Time-Dependent Dielectric Breakdown Under AC Stress in GaN MIS-HEMTs

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high- k /metal gate last process

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