Time optimal linear schedules for algorithms with uniform dependencies

Shang, Weijia; Fortes, José A. B.

doi:10.1109/arrays.1988.18079

Cited by 43 publications

(45 citation statements)

References 14 publications

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“…Unlike [14] and [16], no communication conflict is introduced by our method. In order to efficiently detect the conflicts, a 2-D integer array of size is used such that…”

Section: ) Mapping Objective Functions: Performancementioning

confidence: 94%

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Kittitornkun

2003

IEEE Trans. VLSI Syst.

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Abstract-Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance.

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“…Unlike [14] and [16], no communication conflict is introduced by our method. In order to efficiently detect the conflicts, a 2-D integer array of size is used such that…”

Section: ) Mapping Objective Functions: Performancementioning

confidence: 94%

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Kittitornkun

2003

IEEE Trans. VLSI Syst.

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“…Unlike [19,20], no communication conflict is introduced by our method. In order to efficiently detect the conflicts, a 2D integer array A of size N PE × N cycle is used,…”

Section: Mapping Conflictmentioning

confidence: 94%

Efficient Implementation of Nested-Loop Multimedia Algorithms

Kittitornkun

2001

EURASIP J. Adv. Signal Process.

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A novel dependence graph representation called the multiple-order dependence graph for nested-loop formulated multimedia signal processing algorithms is proposed. It allows a concise representation of an entire family of dependence graphs. This powerful representation facilitates the development of innovative implementation approach for nested-loop formulated multimedia algorithms such as motion estimation, matrix-matrix product, 2D linear transform, and others. In particular, algebraic linear mapping (assignment and scheduling) methodology can be applied to implement such algorithms on an array of simple-processing elements. The feasibility of this new approach is demonstrated in three major target architectures: application-specific integrated circuit (ASIC), field programmable gate array (FPGA), and a programmable clustered VLIW processor.

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“…As far as the scheduling of tiles is concerned, we apply linear scheduling techniques [19]. Central to linear scheduling is the notion of the scheduling vector Π.…”

Section: Tiling Scheduling and Mappingmentioning

confidence: 99%

“…In this case we employ a 1-dimensional processor array and all computations along the first dimension are mapped to the same processor. The straightforward linear schedule for the dependences of our problem that minimizes the total parallel execution steps [19] …”

Section: Schedulingmentioning

confidence: 99%

Overlapping computation and communication in SMT clusters with commodity interconnects

Goumas

Anastopoulos

Koziris

et al. 2009

2009 IEEE International Conference on Cluster Computing and Workshops

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Abstract-In this paper we focus on optimizing the performance in a cluster of Simultaneous Multithreading (SMT) processors connected with a commodity interconnect (e.g. Gbit Ethernet), by applying overlapping of computation with communication. As a test case we consider the parallelized advection equation and discuss the steps that need to be followed to semantically allow overlapping to occur. We propose an implementation based on the concept of Helper Threading that distributes computation and communication in the two sibling threads of an SMT processor, thus creating an asymmetric pair of execution patterns in each hardware context. Our experimental results in an 8-node cluster interconnected with commodity Gbit Ethernet demonstrate that the proposed implementation is able to achieve substantial performance improvements that can exceed 20% in some cases, by efficiently utilizing the available resources of the SMT processors.

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Time optimal linear schedules for algorithms with uniform dependencies

Cited by 43 publications

References 14 publications

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Efficient Implementation of Nested-Loop Multimedia Algorithms

Overlapping computation and communication in SMT clusters with commodity interconnects

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