Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms

Abstract

This work focuses on the time-predictable execution of Deep Neural Networks (DNNs) accelerated on FPGA Systemon-Chips (SoCs). The modern DPU accelerator by Xilinx is considered. An extensive profiling campaign targeting the Zynq Ultrascale+ platform has been performed to study the execution behavior of the DPU when accelerating a set of state-of-the-art DNNs for Advanced Driver Assistance Systems (ADAS). Based on the profiling, an execution model is proposed and then used to derive a response-time analysis. A custom FPGA module named DICTAT is also proposed to improve the predictability of the acceleration of DNNs and tighten the analytical bounds. A rich set of experimental results based on both analytical bounds and measurements from the target platform is finally presented to assess the effectiveness and the performance of the proposed approach on ADAS applications.

Time Predictable Modeling Method for GPU Architecture with SIMT and Cache Miss Awareness

“…They obtained a large amount of data, conducted architecture modeling, and obtained the voltage and frequency that achieved the best performance for each program on different hardware platforms [7] . Restuccia and Biondi conducted architecture modeling for DNN accelerators deployed on FPGA, mainly considering bus conflicts, memory access, OCM, and self-made hardware to analyze and predict the worst-case execution time of DNN programs more accurately [8] . Hong and Kim proposed a comprehensive architecture model to analyze the power consumption and performance of GPUs [9] .…”

UML-Based Design Flow for Systems with Neural Networks

“…Recent approaches with Xilinx FPGAs have shifted from ad-hoc accelerators to using Xilinx's Deep-learning Processing Units (DPUs) for efficient AI service implementation. Various alternatives, including [14], [15], [16], and [17], employ DPUbased CNN models on FPGAs for hardware acceleration.…”