Time-Predictable Out-of-Order Execution for Hard Real-Time Systems

Concurrency and Computation

2011

SUMMARY Hard real‐time systems need a time‐predictable computing platform to enable static worst‐case execution time (WCET) analysis. All performance‐enhancing features need to be WCET analyzable. However, standard data caches containing heap‐allocated data are very hard to analyze statically. In this paper we explore a new object cache design, which is driven by the capabilities of static WCET analysis. Simulations of standard benchmarks estimating the expected average case performance usually drive computer architecture design. The design decisions derived from this methodology do not necessarily result in a WCET analysis‐friendly design. Aiming for a time‐predictable design, we therefore propose to employ WCET analysis techniques for the design space exploration of processor architectures. We evaluated different object cache configurations using static analysis techniques. The number of field accesses that can be statically classified as hits is considerable. The analyzed number of cache miss cycles is 3–46% of the access cycles needed without a cache, which agrees with trends obtained using simulations. Standard data caches perform comparably well in the average case, but accesses to heap data result in overly pessimistic WCET estimations. We therefore believe that an early architecture exploration by means of static timing analysis techniques helps to identify configurations suitable for hard real‐time systems. Copyright © 2011 John Wiley & Sons, Ltd.

Section: Time-predictable Computer Architecturementioning

confidence: 99%

Worst‐case execution time analysis‐driven object cache design

Huber

Puffitsch

Concurrency and Computation

2011

“…The number of copies from external memory is TC mc . For each program execution we computed the ratio TC spm TC mc (2) and plotted its value on the histogram shown in Figure 2. Larger WCETs are of course undesirable, so our results here show us that M$ is either preferable to (or the same as) SPM.…”

Section: Single-path Programsmentioning

confidence: 99%

“…Recent trends towards time-predictable computer architectures [1], [2], [3] have led to the parallel development of two new types of local memory for storing instructions: a scratchpad memory (SPM) and a method cache (M$). Local instruction memory is nothing new, as instruction caches have been in use for decades, but caches present problems for worstcase execution time (WCET) analysis, which is necessary in a time-predictable architecture to ensure that all tasks will meet their deadlines.…”

Section: Introductionmentioning

confidence: 99%

WCET-Based Comparison of an Instruction Scratchpad and a Method Cache

Whitham

2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing

2014

Self Cite

Abstract-This paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worstcase execution time (WCET) and the estimated WCET bound of programs using either an SPM or a method cache, using large numbers of randomly generated programs. For these programs, we find that a method cache is preferable to an SPM if the true WCET is used, because it leads to execution times that are no greater than those for SPM, and are often lower. However, we also find that analytical pessimism is a significant problem for a method cache. If WCET bounds are derived by analysis, the WCET bounds for an instruction SPM are often lower than the bounds for a method cache. This means that an SPM may be preferable in practical systems.

“…Whitham and Audsley present modifications to out-of-order processors to achieve time-predictable operation [27]. Virtual traces allow static WCET analysis, which is performed before execution.…”

Section: E York Rts Groupmentioning

confidence: 99%

Is time predictability quantifiable?

2012 International Conference on Embedded Computer Systems (SAMOS)

2012

Abstract-Computer architects and researchers in the realtime domain start to investigate processors and architectures optimized for real-time systems. Optimized for real-time systems means time predictable, i.e., architectures where it is possible to statically derive a tight bound of the worst-case execution time.To compare different approaches we would like to quantify time predictability. That means we need to measure time predictability. In this paper we discuss the different approaches for these measurements and conclude that time predictability is practically not quantifiable. We can only compare the worst-case execution time bounds of different architectures.