Time-sensitivity-aware shared cache architecture for multi-core embedded systems

Lee, Myoungjun; Kim, Soontae

doi:10.1007/s11227-019-02891-w

Cited by 3 publications

(4 citation statements)

References 40 publications

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“…However, fixed-size partitions cause low cache utilization and consequently reduced performance. On the other hand, in dynamic partitioning techniques, the size of Scheduling algorithms Temporal Hardware HRT [69] Memory request throttling Temporal Software SRT/HRT [74]- [77] Predictable DRAM Controllers Predictable Controller Hardware SRT/HRT [78], [81], [82] Bank Partitioning Spatial Software AVG [60] Channel Partitioning Spatial Soft/Hard AVG [80] Page Policy Control Spatial Soft/Hard AVG [83] Page Policy Control Spatial None AVG [84] Bank Partitioning Spatial None AVG [85] Decoupled Direct Access Spatial Hardware AVG [42] Scheduling algorithms Temporal None AVG [86] Task allocation Temporal Software AVG the allocated cache partitions varies during runtime, giving high cache utilization and causing lower predictability [98]. Furthermore, cache partitioning techniques can be characterized as index-based partitioning and way-based partitioning based on the structure of a set-associative cache.…”

Section: B Cache Interferencementioning

confidence: 99%

“…Lee et al [98] presented a dead-block-based cache partitioning technique on a new shared LLC architecture. The proposal focuses on reducing the deadline miss rate of Timesensitive tasks (TSTs).…”

Section: B Cache Interferencementioning

confidence: 99%

“…Proposals for index-based cache partitioning employ hardware-based or software-based mechanisms. For example, the hardware-based approach by Lee et al [98] uses a cache partitioning technique that considers the memory access characteristics and time-sensitivity of tasks. The proposed scheme requires task profiling.…”

Section: ) Summarymentioning

confidence: 99%

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A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.INDEX TERMS Real-time systems, architecture, multicore, timing analysis, schedulability analysis, WCET, co-runner interference.

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Section: B Cache Interferencementioning

confidence: 99%

Section: B Cache Interferencementioning

confidence: 99%

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A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

et al. 2022

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“…A shared LLC design that takes time sensitivity into account was suggested in [15] to address these issues. To begin, the suggested LLC architecture may be able to recognize TST data and instructions through incorporating a timesensitivity indicator bit into every cache block.…”

Section: Related Workmentioning

confidence: 99%

Examining partitioned caches performance in heterogeneous multi-core processors

Yenugula

2022

Int. J. Commun. Inf. Technol.

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The last-level cache (LLC) is shared by many distinct kinds of cores in asymmetric multi-core systems. There is greater rivalry in the LLC since different core types have different memory access needs. Our new technique for replacing the split cache, HAPC, takes heterogeneity into account. To improve coreto-core interference, this method uses cache partitioning. In multithreaded applications, it guides the replacement strategy by monitoring the shared reuse state of every cache block inside the partition during runtime. This ensures that cache blocks shared among different cores are maintained. For huge cores to make more efficient LLC visits, cache replacement algorithms generally modify the leftover state while preserving cache blocks needed by them. This approach takes into consideration the fact that heterogeneous cores have different memory accesses to LLC. In comparison to the state-of-the-art cache substitute's algorithms, LRU and SRCP, HAPC can greatly enhance the performance of large cores when running multithreaded applications, with almost no impact on small cores, leading to an overall improvement in system performance.

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Application of GMM Model Adaptation Algorithm Based on Embedded System Architecture in Vocal Music Segmentation

Liu

2022

2022 International Conference on Artificial Intelligence of Things and Crowdsensing (AIoTCs)

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Time-sensitivity-aware shared cache architecture for multi-core embedded systems

Cited by 3 publications

References 40 publications

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

Examining partitioned caches performance in heterogeneous multi-core processors

Application of GMM Model Adaptation Algorithm Based on Embedded System Architecture in Vocal Music Segmentation

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