2018 International Conference on Advanced Science and Engineering (ICOASE) 2018
DOI: 10.1109/icoase.2018.8548825
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Time Sharing Based Parallel Implementation of CNN on Low Cost FPGA

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“…Some works target the design of DNN or RNN units on FPGA showing significant acceleration and power efficiency against conventional processor architecture [31,32]. To reduce the resources required for implementation, a time sharing based parallel implementation of CNN could be used [33] or optimized network operators [34]. For a deeper analysis, refer to the online tool [35] that compares NN accelerators on several hardware platforms (FPGA, ASIC and GPU) in terms of speed and power consumption.…”
Section: IVmentioning
confidence: 99%
“…Some works target the design of DNN or RNN units on FPGA showing significant acceleration and power efficiency against conventional processor architecture [31,32]. To reduce the resources required for implementation, a time sharing based parallel implementation of CNN could be used [33] or optimized network operators [34]. For a deeper analysis, refer to the online tool [35] that compares NN accelerators on several hardware platforms (FPGA, ASIC and GPU) in terms of speed and power consumption.…”
Section: IVmentioning
confidence: 99%