Time-to-digital converters and histogram builders in SPAD arrays for pulsed-LiDAR

Sesta, Vincenzo; Incoronato, Alfonso; Madonini, Francesca; Villa, Federica

doi:10.1016/j.measurement.2023.112705

Cited by 8 publications

(2 citation statements)

References 81 publications

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“…In the scientific literature and in the industrial field, there are various architectures of TDCs implementable in both ASICs [16] and FPGAs [13]. Regardless of the type of structure, a TDC assigns a timestamp, referring to the clock with which the TDC is powered, to the occurrence of a low-high and/or high-low transition on the inputs.…”

Section: Backgroundsmentioning

confidence: 99%

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

Garzetti,

Bonanno,

Lusardi

et al. 2024

Electronics

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Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a “Virtual Delay” to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a “Virtual Dead-Time” to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation.

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Section: Backgroundsmentioning

confidence: 99%

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

Garzetti,

Bonanno,

Lusardi

et al. 2024

Electronics

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show abstract

“…The main issue with this approach is the estimation of the parameter α, which depends on λ B and λ S , the latter being affected by a high level of uncertainty since it is related to the intensity of the laser echo. Because the total number of photons detected in the time interval [0, T acq ] is a Poisson random variable with average λ B T acq + Ntot for the parameter α defined in (10). By replacing the parameters µ and α with their estimates ttot and α in formula (11), we obtain the following estimator for ToF:…”

Section: Mathematical Analysismentioning

confidence: 99%

Histogram-Less LiDAR Through SPAD Response Linearization

Tontini,

Mazzucchi,

Passerone

et al. 2024

IEEE Sensors J.

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We present a new method to acquire the 3D information from a SPAD-based direct-Time-of-Flight (d-ToF) imaging system which does not require the construction of a histogram of timestamps and can withstand high flux operation regime. The proposed acquisition scheme emulates the behavior of a SPAD detector with no distortion due to dead time, and extracts the ToF information by a simple average operation on the photon timestamps ensuring ease of integration in a dedicated sensor and scalability to large arrays. The method is validated through a comprehensive mathematical analysis, whose predictions are in agreement with a numerical Monte Carlo model of the problem. Finally, we show the validity of the predictions in a real d-ToF measurement setup under challenging background conditions well beyond the typical pile-up limit of 5% detection rate up to a distance of 3.8 m.

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Line feature based self-calibration method for dual-axis scanning LiDAR system

Wang,

Li,

et al. 2024

Measurement

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Time-to-digital converters and histogram builders in SPAD arrays for pulsed-LiDAR

Cited by 8 publications

References 81 publications

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

Histogram-Less LiDAR Through SPAD Response Linearization

Line feature based self-calibration method for dual-axis scanning LiDAR system

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