Timing abstraction of intellectual property blocks

Venkatesh, Svetha; Palermo, Robert; Mortazavi, Mohammad; Sakallah, Karem A.

doi:10.1109/cicc.1997.606593

Cited by 19 publications

(13 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fortunately, today, there already exists a number of quality works on the generation of timing abstraction of IP blocks or macros. Some notable works are reported in [2]- [8].…”

Section: Introductionmentioning

confidence: 99%

A hierarchical approach towards system level static timing verification of SoCs

Chakraborty

Chowdhury

2009

2009 IEEE International Conference on Computer Design

View full text Add to dashboard Cite

Abstract-The high complexity and the core diversities make timing verification of an entire flattened SoC design a tedious process. In this paper, at first the various timing issues related to modular SoC verification have been investigated and then a bottom-up hierarchical approach of verifying the system level timing of an SoC, is presented. The timing abstractions of the cores are assumed to be provided by the core vendors. The interconnection delays of the SoC may be extracted from the SDF file generated after post layout simulation. The hierarchical approach provides a fast and systematic way of timing verification, as opposed to the flattened approach. Experiments were conducted on synthetic SoCs, using ISCAS benchmark circuits as cores. Results validate the claim of the proposed approach.

show abstract

“…Fortunately, today, there already exists a number of quality works on the generation of timing abstraction of IP blocks or macros. Some notable works are reported in [2]- [8].…”

Section: Introductionmentioning

confidence: 99%

A hierarchical approach towards system level static timing verification of SoCs

Chakraborty

Chowdhury

2009

2009 IEEE International Conference on Computer Design

View full text Add to dashboard Cite

show abstract

“…In either case, the grey-box model has the disadvantage of exposing the circuit's structure and complexity to higher levels of analysis which is potentially inefficient as well as inapplicable in cases where no part of the intellectual property can be revealed. In contrast, our approach is a black-box type of modeling, based on a technique called clock modeling originally proposed in [6]. Through processing of the internal timing constraints, the clock modeling approach reduces all the timing constraints of a sequential block into a small set of constraints in terms of the circuit's clock parameters, those being clock pulse widths and phase separations.…”

Section: Characterization Of Sequential Blocksmentioning

confidence: 99%

“…The limitation of the method described in [6] is that it is based on topological delay analysis. Thus the clock models it produces can be pessimistic because of false paths.…”

Section: Characterization Of Sequential Blocksmentioning

confidence: 99%

See 1 more Smart Citation

An advanced timing characterization method using mode dependency

Yalcin¹,

Palermo²,

Mortazavi³

et al.

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)

Self Cite

View full text Add to dashboard Cite

show abstract

“…There are previous researches dealing with the timing macromodeling of IP blocks, and all of them are based on the concept of path delay [1,2,3,4,5,6]. The simplest of such models is the "pin-to-pin" delay model used to characterize standard cells and other complex combinational circuits.…”

Section: Introductionmentioning

confidence: 99%

Timing macro-modeling of IP blocks with crosstalk

Chen

Zhou

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

View full text Add to dashboard Cite

With the increase of design complexities and the decrease of minimal feature sizes, IP reuse is becoming a common practice while crosstalk is becoming a critical issue that must be considered. This paper presents two macro-models for specifying the timing behaviors of combinational hard IP blocks with crosstalk effects. The gray-box model keeps a coupling graph and lists the conditions on relative input arrival time combinations for couplings not to take effect. The black-box model stores the output response windows for a basic set of relative input arrival time combinations, and computes the output arrival time for any given input arrival time combination through the union of some combinations in the basic set. Both macro-models are conservative, and can greatly reduce the pessimism existing in the conventional "pin-to-pin" model. This is the first work to deal with timing macromodeling of combinational hard IP blocks with the consideration of crosstalk effects. IntroductionWith the progress of deep sub-micron technologies, shrinking geometries have led to a reduction in self-capacitance of wires. Meanwhile coupling capacitances have increased as wires have a larger aspect ratio and are brought closer together. For present day processes, the coupling capacitance can be as large as the sum of the area capacitance and the fringing capacitance, and the trends indicate that the role of coupling capacitance will be even more dominant in the future as feature sizes shrink. This makes crosstalk a major problem in IC design. Crosstalk introduces noise between adjacent wires, and even alters the functions of circuits. If an aggressor and a victim switch simultaneously on the same direction, the victim will speed up. Likewise, if an aggressor and a victim switch on the opposite directions, the victim will slow down.With the growing complexity of VLSI systems, the intellectual property (IP) reuse is becoming a common practice. There are previous researches dealing with the timing macromodeling of IP blocks, and all of them are based on the concept of path delay [1,2,3,4,5,6]. The simplest of such models is the "pin-to-pin" delay model used to characterize standard cells and other complex combinational circuits. For example, given a simple combinational circuit shown in Figure 1(a), its "pin-to-pin" delay model is shown in Figure 1(b). The numbers shown on each arc give the minimal and maximal delays from one pin to another. In this case, if a(x) and A(x) are used to represent the earliest and latest arrival time of signal x, respectively, we haveTo model a sequential circuit with memory elements, the "pinto-pin" model is extended to include timing constraints from a clock pin to an input pin (to model setup and hold conditions) and delay arcs from a clock pin to an output pin (to model the latch output to circuit output delay) [1]. Functionality may also be used to reduce the pessimism in these models [5,6]. * This work was supported by NSF under CCR-0238484. Unfortunately, coupling totally destroys the path delay...

show abstract

Timing abstraction of intellectual property blocks

Cited by 19 publications

References 6 publications

A hierarchical approach towards system level static timing verification of SoCs

A hierarchical approach towards system level static timing verification of SoCs

An advanced timing characterization method using mode dependency

Timing macro-modeling of IP blocks with crosstalk

Contact Info

Product

Resources

About