Timing analysis of erroneous systems

Abstract

Erroneous systems allow timing errors to occur during execution, but use measures to ensure continued operation through changes in operating parameters (voltage and frequency), error correction at various levels of the system, or ensuring controlled occurrence of errors to perform approximate computing. In this paper, we are interested in characterization of error behavior at the level of instructions and programs. We propose Inter-and Intra-Program Variation as measures of error rate variability in different programs and among instructions of a program, respectively. We also characterize the error rate variation caused by the program input data and show that it is comparable to other sources of variability such as process variation. Finally, we present an analysis of the physical location of errors in hardware, identify regions in which most of the errors occur, and how different programs change the distribution of errors among these regions. In order to enable reliable timing analysis of large programs, we propose Clustered Timing Model (CTM), a high level timing model based on clustering functionally similar timing paths of the processor, and develop a CTM for LEON3, a representative in-order RISC processor. The accuracy of the model is verified using our variation-aware timing analysis framework with an average error of 3.9% (max. 6.7%) across a wide range of voltage-temperature corners.

Light-weight one-cycle timing error correction based on hardware software co-design

“…Most of the timing errors are distributed in execution units [17,18,19,22,24]. For example, the authors in [17] present that errors in the LEON3 processor are distributed between ALU (arithmetic and logic unit, 24%), address generation (25%), result bus (29%) and control logic (22%). The key reason is that critical paths are usually distributed in data paths of execution units, which are mainly composed of large combinational logic, such as adders and multipliers.…”

“…To detect each hot instruction and calculate its error rate, TEPM integrates the clustered timing model [17] into a cycle-accurate pipeline simulator. The model collects stage-level transition information from the simulator, and then uses the information to calculate the maximum path delay.…”

“…Based on the locality of timing errors in instruction level [17,18,19,20,21,22], this work proposes a novel hardware-software co-designed EDAC approach to achieve one-cycle error correction. It applies TEDPI (timing error deletion programming interface) to pre-detect most of the errors through an offline timing error prediction model, and pre-correct them at compilation time by using a specially designed timing error avoidance instruction.…”

Graph-based dynamic analysis: Efficient characterization of dynamic timing and activity distributions

“…In contrast, our technique captures the path profile of a workload (or instruction sequence) in a single gate-level simulation, and the error rates at different operating points can be computed significantly faster by recomputing gate delays and performing STA. [13] proposes a clustered timing model to capture the dynamic delay distribution of a processor. Their approach requires manual analysis of the architecture and produces inexact results because of architectural approximations.…”

Performance Analysis of Timing-Speculative Processors

“…Finally, it is useful to consider input data (running code and its input in case of processors) as variation sources. Studies show that changing input data to a single program can cause performance variations comparable in magnitude to those caused by other variability sources such as process variation [2].…”